Linux CXL
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From: sashiko-bot@kernel.org
To: alejandro.lucero-palau@amd.com
Cc: linux-cxl@vger.kernel.org
Subject: Re: [PATCH v28 1/5] sfc: add cxl support
Date: Fri, 19 Jun 2026 17:24:43 +0000	[thread overview]
Message-ID: <20260619172443.7555F1F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260618181806.118745-2-alejandro.lucero-palau@amd.com>

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] Probe error path skips `efx_fini_io` cleanup when `efx_cxl_init` fails, leaking PCI I/O mappings and regions.
--

commit f3841c5aaa83257b810b3b73eb3877f94fb0a964
Author: Alejandro Lucero <alucerop@amd.com>

sfc: add cxl support

This commit adds CXL initialization based on the new CXL API for accel
drivers and makes it dependent on kernel CXL configuration.

> diff --git a/drivers/net/ethernet/sfc/efx.c b/drivers/net/ethernet/sfc/efx.c
> index 8f136a11d3968..da008462096d0 100644
> --- a/drivers/net/ethernet/sfc/efx.c
> +++ b/drivers/net/ethernet/sfc/efx.c
[ ... ]
> @@ -1190,6 +1193,17 @@ static int efx_pci_probe(struct pci_dev *pci_dev,
>  	if (rc)
>  		goto fail2;
>  
> +	/* A successful cxl initialization implies a CXL region created to be
> +	 * used for PIO buffers. If there is no CXL support legacy PIO buffers
> +	 * defined at specific PCI BAR regions will be used. If there is CXL
> +	 * support and the cxl initialization fails, the driver probe fails.
> +	 */
> +	rc = efx_cxl_init(probe_data);
> +	if (rc) {
> +		pci_err(pci_dev, "CXL initialization failed with error %d\n", rc);
> +		goto fail2;

[Severity: High]
Does this leak PCI I/O mappings and regions if efx_cxl_init() fails?

If efx_cxl_init() fails, the code jumps directly to fail2:

	rc = efx_init_io(...)
	if (rc)
		goto fail2;

	rc = efx_cxl_init(probe_data);
	if (rc) {
		...
		goto fail2;
	...
 fail3:
	efx_fini_io(efx);
 fail2:
	efx_cxl_exit(probe_data);
	efx_fini_struct(efx);

Because efx_init_io() completes successfully just prior to this, shouldn't
this error path jump to fail3 so that the I/O resources and PCI device
enable state are properly cleaned up?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260618181806.118745-1-alejandro.lucero-palau@amd.com?part=1

  parent reply	other threads:[~2026-06-19 17:24 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-06-18 18:18 [PATCH v28 0/5] Type2 device basic support alejandro.lucero-palau
2026-06-18 18:18 ` [PATCH v28 1/5] sfc: add cxl support alejandro.lucero-palau
2026-06-19 13:12   ` Edward Cree
2026-06-19 17:24   ` sashiko-bot [this message]
2026-06-18 18:18 ` [PATCH v28 2/5] cxl/sfc: Map cxl regs alejandro.lucero-palau
2026-06-19 13:14   ` Edward Cree
2026-06-19 17:24   ` sashiko-bot
2026-06-18 18:18 ` [PATCH v28 3/5] cxl/sfc: Initialize dpa without a mailbox alejandro.lucero-palau
2026-06-19 13:15   ` Edward Cree
2026-06-19 17:24   ` sashiko-bot
2026-06-18 18:18 ` [PATCH v28 4/5] sfc: obtain and map cxl range using devm_cxl_probe_mem alejandro.lucero-palau
2026-06-18 23:05   ` Dave Jiang
2026-06-19 13:20   ` Edward Cree
2026-06-19 17:24   ` sashiko-bot
2026-06-18 18:18 ` [PATCH v28 5/5] sfc: support pio mapping based on cxl alejandro.lucero-palau
2026-06-18 23:06   ` Dave Jiang
2026-06-19 13:23   ` Edward Cree
2026-06-19 17:24   ` sashiko-bot

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