[PATCH v2 0/2] Export pcie_aer_is_native() to AER namespace

[PATCH v2 0/2] Export pcie_aer_is_native() to AER namespace

[Raag Jadav]

This series adds xe driver as a new user of pcie_aer_is_native() and
changes pcie_aer_is_native() export namespace to AER instead of CXL.
Detailed description in commit message.

v2: Change pcie_aer_is_native() export namespace to AER (Lukas)

Raag Jadav (2):
  PCI/AER: Export pcie_aer_is_native() to AER namespace
  drm/xe/ras: Enable SGUnit PCIe error reporting

 drivers/cxl/port.c          |  1 +
 drivers/gpu/drm/xe/xe_ras.c | 14 ++++++++++++++
 drivers/pci/pcie/aer.c      |  2 +-
 3 files changed, 16 insertions(+), 1 deletion(-)

-- 
2.43.0

[PATCH v2 1/2] PCI/AER: Export pcie_aer_is_native() to AER namespace

[Raag Jadav]

pcie_aer_is_native() was originally exported to CXL namespace in commit
49f776724e64 ("PCI/AER: Export pcie_aer_is_native()"). This is a bit
misleading as the symbol or its underlying implementation does not reflect
any distinguishable CXL functionality.

Change this and export pcie_aer_is_native() to AER namespace, which is
cleaner and more suitable for its implementation.

Suggested-by: Lukas Wunner <lukas@wunner.de>
Signed-off-by: Raag Jadav <raag.jadav@intel.com>
---
 drivers/cxl/port.c     | 1 +
 drivers/pci/pcie/aer.c | 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/cxl/port.c b/drivers/cxl/port.c
index 99cf77b6b699..00f675163b3d 100644
--- a/drivers/cxl/port.c
+++ b/drivers/cxl/port.c
@@ -340,5 +340,6 @@ module_exit(cxl_port_exit);
 
 MODULE_DESCRIPTION("CXL: Port enumeration and services");
 MODULE_LICENSE("GPL v2");
+MODULE_IMPORT_NS("AER");
 MODULE_IMPORT_NS("CXL");
 MODULE_ALIAS_CXL(CXL_DEVICE_PORT);
diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c
index c4fd9c0b2a54..8660b18bac8b 100644
--- a/drivers/pci/pcie/aer.c
+++ b/drivers/pci/pcie/aer.c
@@ -248,7 +248,7 @@ int pcie_aer_is_native(struct pci_dev *dev)
 
 	return pcie_ports_native || host->native_aer;
 }
-EXPORT_SYMBOL_NS_GPL(pcie_aer_is_native, "CXL");
+EXPORT_SYMBOL_NS_GPL(pcie_aer_is_native, "AER");
 
 static int pci_enable_pcie_error_reporting(struct pci_dev *dev)
 {
-- 
2.43.0

[PATCH v2 2/2] drm/xe/ras: Enable SGUnit PCIe error reporting

[Raag Jadav]

SGUnit as a PCI endpoint is not AER capable and requires explicit
programming of error reporting bits in DevCtl register of it's config
space for upstream error propagation. Hack it.

While at it, add native AER sanity check for upstream port before
programming SGUnit register.

This is as per pci_enable_pcie_error_reporting() logic implemented
in PCIe AER driver.

Signed-off-by: Raag Jadav <raag.jadav@intel.com>
Reviewed-by: Lukas Wunner <lukas@wunner.de>
---
 drivers/gpu/drm/xe/xe_ras.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c
index de4cb9ef7355..c4b5c0b5eb0d 100644
--- a/drivers/gpu/drm/xe/xe_ras.c
+++ b/drivers/gpu/drm/xe/xe_ras.c
@@ -3,6 +3,8 @@
  * Copyright © 2026 Intel Corporation
  */
 
+#include <linux/aer.h>
+
 #include "xe_debugfs.h"
 #include "xe_device.h"
 #include "xe_drm_ras.h"
@@ -234,6 +236,9 @@ static struct pci_dev *find_usp_dev(struct pci_dev *pdev)
 	return pci_upstream_bridge(vsp);
 }
 
+#define PCI_EXP_AER_FLAGS	(PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE | \
+				 PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE)
+
 static void ras_usp_aer_init(struct xe_device *xe)
 {
 	struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
@@ -251,6 +256,14 @@ static void ras_usp_aer_init(struct xe_device *xe)
 		return;
 	}
 
+	if (!pcie_aer_is_native(usp)) {
+		dev_warn(&usp->dev, "No native AER support\n");
+		return;
+	}
+
+	pcie_capability_set_word(pdev, PCI_EXP_DEVCTL, PCI_EXP_AER_FLAGS);
+	pci_save_state(pdev);
+
 	/*
 	 * Clear any stale Uncorrectable Internal Error Status event in Uncorrectable Error
 	 * Status Register.
@@ -279,6 +292,7 @@ static void ras_usp_aer_init(struct xe_device *xe)
 	pci_save_state(usp);
 	dev_dbg(&usp->dev, "Uncorrectable Internal Errors downgraded and unmasked\n");
 }
+MODULE_IMPORT_NS("AER");
 
 static void ras_send_error_event(struct xe_device *xe, u8 severity, u8 component)
 {
-- 
2.43.0

Re: [PATCH v2 1/2] PCI/AER: Export pcie_aer_is_native() to AER namespace

[sashiko-bot]

> pcie_aer_is_native() was originally exported to CXL namespace in commit
> 49f776724e64 ("PCI/AER: Export pcie_aer_is_native()"). This is a bit
> misleading as the symbol or its underlying implementation does not reflect
> any distinguishable CXL functionality.
> 
> Change this and export pcie_aer_is_native() to AER namespace, which is
> cleaner and more suitable for its implementation.
> 
> Suggested-by: Lukas Wunner <lukas@wunner.de>
> Signed-off-by: Raag Jadav <raag.jadav@intel.com>

Sashiko has reviewed this patch and found no issues. It looks great!

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260825054312.1319951-1-raag.jadav@intel.com?part=1

Re: [PATCH v2 2/2] drm/xe/ras: Enable SGUnit PCIe error reporting

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:

Pre-existing issues:
- [High] Unprotected call to pci_save_state() on a shared upstream device can cause a data race.
--

--- Patch [2]: [PATCH v2 2/2] drm/xe/ras: Enable SGUnit PCIe error reporting ---
commit 4e1cc07b97a799fd7dc8e01bed43ae859ed4cc97
Author: Raag Jadav <raag.jadav@intel.com>

drm/xe/ras: Enable SGUnit PCIe error reporting

This commit hacks the SGUnit config space to program error reporting bits
in the DevCtl register since it is not AER capable. It also adds a native
AER sanity check for the upstream port.

> diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c
> index d25d25f775310..3118c713c1186 100644
> --- a/drivers/gpu/drm/xe/xe_ras.c
> +++ b/drivers/gpu/drm/xe/xe_ras.c
[ ... ]
> @@ -279,6 +292,7 @@ static void ras_usp_aer_init(struct xe_device *xe)
>  	/* Unmask Uncorrectable Internal Error */
>  	pci_clear_and_set_config_dword(usp, aer_cap + PCI_ERR_UNCOR_MASK, PCI_ERR_UNC_INTN, 0);
>  
>  	pci_save_state(usp);

[Severity: High]
This isn't a bug introduced by this patch, but is it safe to call
pci_save_state(usp) on a shared upstream device without locking?

Looking at ras_usp_aer_init() in drivers/gpu/drm/xe/xe_ras.c, if multiple
SGUnits (endpoints) under the same upstream switch port are probed or
initialized concurrently (for example, via async probe of multiple GPU tiles
or functions), they will concurrently execute pci_save_state(usp) on the same
shared upstream port without acquiring the device lock.

Could this lead to a data race, writing directly to usp->saved_config_space
and other PM state arrays simultaneously, and corrupt the PCI PM state for the
upstream switch port?

>  	dev_dbg(&usp->dev, "Uncorrectable Internal Errors downgraded and unmasked\n");
>  }
> +MODULE_IMPORT_NS("AER");

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260825054312.1319951-1-raag.jadav@intel.com?part=2

Re: [PATCH v2 1/2] PCI/AER: Export pcie_aer_is_native() to AER namespace

[Rodrigo Vivi]

On Tue, Aug 25, 2026 at 11:12:50AM +0530, Raag Jadav wrote:
> pcie_aer_is_native() was originally exported to CXL namespace in commit
> 49f776724e64 ("PCI/AER: Export pcie_aer_is_native()"). This is a bit
> misleading as the symbol or its underlying implementation does not reflect
> any distinguishable CXL functionality.
> 
> Change this and export pcie_aer_is_native() to AER namespace, which is
> cleaner and more suitable for its implementation.
> 
> Suggested-by: Lukas Wunner <lukas@wunner.de>
> Signed-off-by: Raag Jadav <raag.jadav@intel.com>
> ---
>  drivers/cxl/port.c     | 1 +
>  drivers/pci/pcie/aer.c | 2 +-

PCI and CXL folks, ack to get this through drm-next branches towards 7.4?
Or any of you wanting to pull this through your trees for 7.3-rc1?

Thanks,
Rodrigo.

btw:

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

>  2 files changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/cxl/port.c b/drivers/cxl/port.c
> index 99cf77b6b699..00f675163b3d 100644
> --- a/drivers/cxl/port.c
> +++ b/drivers/cxl/port.c
> @@ -340,5 +340,6 @@ module_exit(cxl_port_exit);
>  
>  MODULE_DESCRIPTION("CXL: Port enumeration and services");
>  MODULE_LICENSE("GPL v2");
> +MODULE_IMPORT_NS("AER");
>  MODULE_IMPORT_NS("CXL");
>  MODULE_ALIAS_CXL(CXL_DEVICE_PORT);
> diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c
> index c4fd9c0b2a54..8660b18bac8b 100644
> --- a/drivers/pci/pcie/aer.c
> +++ b/drivers/pci/pcie/aer.c
> @@ -248,7 +248,7 @@ int pcie_aer_is_native(struct pci_dev *dev)
>  
>  	return pcie_ports_native || host->native_aer;
>  }
> -EXPORT_SYMBOL_NS_GPL(pcie_aer_is_native, "CXL");
> +EXPORT_SYMBOL_NS_GPL(pcie_aer_is_native, "AER");
>  
>  static int pci_enable_pcie_error_reporting(struct pci_dev *dev)
>  {
> -- 
> 2.43.0
> 

Re: [PATCH v2 1/2] PCI/AER: Export pcie_aer_is_native() to AER namespace

[Dave Jiang]

On 8/24/26 10:42 PM, Raag Jadav wrote:
> pcie_aer_is_native() was originally exported to CXL namespace in commit
> 49f776724e64 ("PCI/AER: Export pcie_aer_is_native()"). This is a bit
> misleading as the symbol or its underlying implementation does not reflect
> any distinguishable CXL functionality.
> 
> Change this and export pcie_aer_is_native() to AER namespace, which is
> cleaner and more suitable for its implementation.
> 
> Suggested-by: Lukas Wunner <lukas@wunner.de>
> Signed-off-by: Raag Jadav <raag.jadav@intel.com>

For the CXL part,
Acked-by: Dave Jiang <dave.jiang@intel.com>

You'll need Bjorn's ack for the PCI portion.

> ---
>  drivers/cxl/port.c     | 1 +
>  drivers/pci/pcie/aer.c | 2 +-
>  2 files changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/cxl/port.c b/drivers/cxl/port.c
> index 99cf77b6b699..00f675163b3d 100644
> --- a/drivers/cxl/port.c
> +++ b/drivers/cxl/port.c
> @@ -340,5 +340,6 @@ module_exit(cxl_port_exit);
>  
>  MODULE_DESCRIPTION("CXL: Port enumeration and services");
>  MODULE_LICENSE("GPL v2");
> +MODULE_IMPORT_NS("AER");
>  MODULE_IMPORT_NS("CXL");
>  MODULE_ALIAS_CXL(CXL_DEVICE_PORT);
> diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c
> index c4fd9c0b2a54..8660b18bac8b 100644
> --- a/drivers/pci/pcie/aer.c
> +++ b/drivers/pci/pcie/aer.c
> @@ -248,7 +248,7 @@ int pcie_aer_is_native(struct pci_dev *dev)
>  
>  	return pcie_ports_native || host->native_aer;
>  }
> -EXPORT_SYMBOL_NS_GPL(pcie_aer_is_native, "CXL");
> +EXPORT_SYMBOL_NS_GPL(pcie_aer_is_native, "AER");
>  
>  static int pci_enable_pcie_error_reporting(struct pci_dev *dev)
>  {

Re: [PATCH v2 1/2] PCI/AER: Export pcie_aer_is_native() to AER namespace

[Dave Jiang]

On 8/25/26 7:18 AM, Rodrigo Vivi wrote:
> On Tue, Aug 25, 2026 at 11:12:50AM +0530, Raag Jadav wrote:
>> pcie_aer_is_native() was originally exported to CXL namespace in commit
>> 49f776724e64 ("PCI/AER: Export pcie_aer_is_native()"). This is a bit
>> misleading as the symbol or its underlying implementation does not reflect
>> any distinguishable CXL functionality.
>>
>> Change this and export pcie_aer_is_native() to AER namespace, which is
>> cleaner and more suitable for its implementation.
>>
>> Suggested-by: Lukas Wunner <lukas@wunner.de>
>> Signed-off-by: Raag Jadav <raag.jadav@intel.com>
>> ---
>>  drivers/cxl/port.c     | 1 +
>>  drivers/pci/pcie/aer.c | 2 +-
> 
> PCI and CXL folks, ack to get this through drm-next branches towards 7.4?
> Or any of you wanting to pull this through your trees for 7.3-rc1?

It's not really a fix and with no fixes tag. Also it's not a bug that popped up in the 7.3 merge window. It'll have to be 7.4. I can pull it through CXL when all the appropriate tags show up or you can take it through DRM. Probably more reasonable for the DRM tree given the second patch is what needs the change. Just make it clear to the maintainers how you want to do this.

DJ

> 
> Thanks,
> Rodrigo.
> 
> btw:
> 
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> 
>>  2 files changed, 2 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/cxl/port.c b/drivers/cxl/port.c
>> index 99cf77b6b699..00f675163b3d 100644
>> --- a/drivers/cxl/port.c
>> +++ b/drivers/cxl/port.c
>> @@ -340,5 +340,6 @@ module_exit(cxl_port_exit);
>>  
>>  MODULE_DESCRIPTION("CXL: Port enumeration and services");
>>  MODULE_LICENSE("GPL v2");
>> +MODULE_IMPORT_NS("AER");
>>  MODULE_IMPORT_NS("CXL");
>>  MODULE_ALIAS_CXL(CXL_DEVICE_PORT);
>> diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c
>> index c4fd9c0b2a54..8660b18bac8b 100644
>> --- a/drivers/pci/pcie/aer.c
>> +++ b/drivers/pci/pcie/aer.c
>> @@ -248,7 +248,7 @@ int pcie_aer_is_native(struct pci_dev *dev)
>>  
>>  	return pcie_ports_native || host->native_aer;
>>  }
>> -EXPORT_SYMBOL_NS_GPL(pcie_aer_is_native, "CXL");
>> +EXPORT_SYMBOL_NS_GPL(pcie_aer_is_native, "AER");
>>  
>>  static int pci_enable_pcie_error_reporting(struct pci_dev *dev)
>>  {
>> -- 
>> 2.43.0
>>

Re: [PATCH v2 1/2] PCI/AER: Export pcie_aer_is_native() to AER namespace

[Rodrigo Vivi]

On Tue, Aug 25, 2026 at 08:05:36AM -0700, Dave Jiang wrote:
> 
> 
> On 8/25/26 7:18 AM, Rodrigo Vivi wrote:
> > On Tue, Aug 25, 2026 at 11:12:50AM +0530, Raag Jadav wrote:
> >> pcie_aer_is_native() was originally exported to CXL namespace in commit
> >> 49f776724e64 ("PCI/AER: Export pcie_aer_is_native()"). This is a bit
> >> misleading as the symbol or its underlying implementation does not reflect
> >> any distinguishable CXL functionality.
> >>
> >> Change this and export pcie_aer_is_native() to AER namespace, which is
> >> cleaner and more suitable for its implementation.
> >>
> >> Suggested-by: Lukas Wunner <lukas@wunner.de>
> >> Signed-off-by: Raag Jadav <raag.jadav@intel.com>
> >> ---
> >>  drivers/cxl/port.c     | 1 +
> >>  drivers/pci/pcie/aer.c | 2 +-
> > 
> > PCI and CXL folks, ack to get this through drm-next branches towards 7.4?
> > Or any of you wanting to pull this through your trees for 7.3-rc1?
> 
> It's not really a fix and with no fixes tag. Also it's not a bug that popped up in the 7.3 merge window. It'll have to be 7.4. I can pull it through CXL when all the appropriate tags show up or you can take it through DRM. Probably more reasonable for the DRM tree given the second patch is what needs the change. Just make it clear to the maintainers how you want to do this.

Since it is 7.4 anyway I prefer to take already with drm-next.

CLX and PCI maintainers, ack on that?

> 
> DJ
> 
> > 
> > Thanks,
> > Rodrigo.
> > 
> > btw:
> > 
> > Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > 
> >>  2 files changed, 2 insertions(+), 1 deletion(-)
> >>
> >> diff --git a/drivers/cxl/port.c b/drivers/cxl/port.c
> >> index 99cf77b6b699..00f675163b3d 100644
> >> --- a/drivers/cxl/port.c
> >> +++ b/drivers/cxl/port.c
> >> @@ -340,5 +340,6 @@ module_exit(cxl_port_exit);
> >>  
> >>  MODULE_DESCRIPTION("CXL: Port enumeration and services");
> >>  MODULE_LICENSE("GPL v2");
> >> +MODULE_IMPORT_NS("AER");
> >>  MODULE_IMPORT_NS("CXL");
> >>  MODULE_ALIAS_CXL(CXL_DEVICE_PORT);
> >> diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c
> >> index c4fd9c0b2a54..8660b18bac8b 100644
> >> --- a/drivers/pci/pcie/aer.c
> >> +++ b/drivers/pci/pcie/aer.c
> >> @@ -248,7 +248,7 @@ int pcie_aer_is_native(struct pci_dev *dev)
> >>  
> >>  	return pcie_ports_native || host->native_aer;
> >>  }
> >> -EXPORT_SYMBOL_NS_GPL(pcie_aer_is_native, "CXL");
> >> +EXPORT_SYMBOL_NS_GPL(pcie_aer_is_native, "AER");
> >>  
> >>  static int pci_enable_pcie_error_reporting(struct pci_dev *dev)
> >>  {
> >> -- 
> >> 2.43.0
> >>
> 

Re: [PATCH v2 1/2] PCI/AER: Export pcie_aer_is_native() to AER namespace

[Dave Jiang]

On 8/25/26 8:25 AM, Rodrigo Vivi wrote:
> On Tue, Aug 25, 2026 at 08:05:36AM -0700, Dave Jiang wrote:
>>
>>
>> On 8/25/26 7:18 AM, Rodrigo Vivi wrote:
>>> On Tue, Aug 25, 2026 at 11:12:50AM +0530, Raag Jadav wrote:
>>>> pcie_aer_is_native() was originally exported to CXL namespace in commit
>>>> 49f776724e64 ("PCI/AER: Export pcie_aer_is_native()"). This is a bit
>>>> misleading as the symbol or its underlying implementation does not reflect
>>>> any distinguishable CXL functionality.
>>>>
>>>> Change this and export pcie_aer_is_native() to AER namespace, which is
>>>> cleaner and more suitable for its implementation.
>>>>
>>>> Suggested-by: Lukas Wunner <lukas@wunner.de>
>>>> Signed-off-by: Raag Jadav <raag.jadav@intel.com>
>>>> ---
>>>>  drivers/cxl/port.c     | 1 +
>>>>  drivers/pci/pcie/aer.c | 2 +-
>>>
>>> PCI and CXL folks, ack to get this through drm-next branches towards 7.4?
>>> Or any of you wanting to pull this through your trees for 7.3-rc1?
>>
>> It's not really a fix and with no fixes tag. Also it's not a bug that popped up in the 7.3 merge window. It'll have to be 7.4. I can pull it through CXL when all the appropriate tags show up or you can take it through DRM. Probably more reasonable for the DRM tree given the second patch is what needs the change. Just make it clear to the maintainers how you want to do this.
> 
> Since it is 7.4 anyway I prefer to take already with drm-next.
> 
> CLX and PCI maintainers, ack on that?

I gave the CXL ack. You just need a Bjorn ack. 

> 
>>
>> DJ
>>
>>>
>>> Thanks,
>>> Rodrigo.
>>>
>>> btw:
>>>
>>> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>>>
>>>>  2 files changed, 2 insertions(+), 1 deletion(-)
>>>>
>>>> diff --git a/drivers/cxl/port.c b/drivers/cxl/port.c
>>>> index 99cf77b6b699..00f675163b3d 100644
>>>> --- a/drivers/cxl/port.c
>>>> +++ b/drivers/cxl/port.c
>>>> @@ -340,5 +340,6 @@ module_exit(cxl_port_exit);
>>>>  
>>>>  MODULE_DESCRIPTION("CXL: Port enumeration and services");
>>>>  MODULE_LICENSE("GPL v2");
>>>> +MODULE_IMPORT_NS("AER");
>>>>  MODULE_IMPORT_NS("CXL");
>>>>  MODULE_ALIAS_CXL(CXL_DEVICE_PORT);
>>>> diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c
>>>> index c4fd9c0b2a54..8660b18bac8b 100644
>>>> --- a/drivers/pci/pcie/aer.c
>>>> +++ b/drivers/pci/pcie/aer.c
>>>> @@ -248,7 +248,7 @@ int pcie_aer_is_native(struct pci_dev *dev)
>>>>  
>>>>  	return pcie_ports_native || host->native_aer;
>>>>  }
>>>> -EXPORT_SYMBOL_NS_GPL(pcie_aer_is_native, "CXL");
>>>> +EXPORT_SYMBOL_NS_GPL(pcie_aer_is_native, "AER");
>>>>  
>>>>  static int pci_enable_pcie_error_reporting(struct pci_dev *dev)
>>>>  {
>>>> -- 
>>>> 2.43.0
>>>>
>>

Re: [PATCH v2 2/2] drm/xe/ras: Enable SGUnit PCIe error reporting

[Bjorn Helgaas]

On Tue, Aug 25, 2026 at 11:12:51AM +0530, Raag Jadav wrote:
> SGUnit as a PCI endpoint is not AER capable and requires explicit
> programming of error reporting bits in DevCtl register of it's config
> space for upstream error propagation. Hack it.

s/it's/its/

> While at it, add native AER sanity check for upstream port before
> programming SGUnit register.
> 
> This is as per pci_enable_pcie_error_reporting() logic implemented
> in PCIe AER driver.
> 
> Signed-off-by: Raag Jadav <raag.jadav@intel.com>
> Reviewed-by: Lukas Wunner <lukas@wunner.de>
> ---
>  drivers/gpu/drm/xe/xe_ras.c | 14 ++++++++++++++
>  1 file changed, 14 insertions(+)
> 
> diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c
> index de4cb9ef7355..c4b5c0b5eb0d 100644
> --- a/drivers/gpu/drm/xe/xe_ras.c
> +++ b/drivers/gpu/drm/xe/xe_ras.c
> @@ -3,6 +3,8 @@
>   * Copyright © 2026 Intel Corporation
>   */
>  
> +#include <linux/aer.h>
> +
>  #include "xe_debugfs.h"
>  #include "xe_device.h"
>  #include "xe_drm_ras.h"
> @@ -234,6 +236,9 @@ static struct pci_dev *find_usp_dev(struct pci_dev *pdev)
>  	return pci_upstream_bridge(vsp);
>  }
>  
> +#define PCI_EXP_AER_FLAGS	(PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE | \
> +				 PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE)

Ugh :)  Duplicate of what's in drivers/pci/pci.h.

>  static void ras_usp_aer_init(struct xe_device *xe)
>  {
>  	struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
> @@ -251,6 +256,14 @@ static void ras_usp_aer_init(struct xe_device *xe)
>  		return;
>  	}
>  
> +	if (!pcie_aer_is_native(usp)) {
> +		dev_warn(&usp->dev, "No native AER support\n");
> +		return;
> +	}
> +
> +	pcie_capability_set_word(pdev, PCI_EXP_DEVCTL, PCI_EXP_AER_FLAGS);

The PCI core calls pci_aer_init() for every device, which only calls
pci_enable_pcie_error_reporting() to set PCI_EXP_AER_FLAGS when the
device itself has an AER Capability.

Setting PCI_EXP_AER_FLAGS enables the device to send ERR_* messages
upstream.  *Maybe* enabling those has something to do with whether the
Root Port (the ultimate consumer of those ERR_* messages) supports
AER, but I don't think it is related to whether the device *itself*
has an AER Capability.

It seems to me like the PCI core should do
pci_enable_pcie_error_reporting() independent of whether the device
has an AER Capability.

> +	pci_save_state(pdev);
> +
>  	/*
>  	 * Clear any stale Uncorrectable Internal Error Status event in Uncorrectable Error
>  	 * Status Register.
> @@ -279,6 +292,7 @@ static void ras_usp_aer_init(struct xe_device *xe)
>  	pci_save_state(usp);
>  	dev_dbg(&usp->dev, "Uncorrectable Internal Errors downgraded and unmasked\n");
>  }
> +MODULE_IMPORT_NS("AER");
>  
>  static void ras_send_error_event(struct xe_device *xe, u8 severity, u8 component)
>  {
> -- 
> 2.43.0
>