From: Jonathan Cameron <jic23@kernel.org>
To: Anisa Su <anisa.su887@gmail.com>
Cc: linux-cxl@vger.kernel.org, alison.schofield@intel.com,
dave.jiang@intel.com, gourry@gourry.net, icheng@nvidia.com,
ming.li@zohomail.com, vishal.l.verma@intel.com,
dave@stgolabs.net, benjamin.cheatham@amd.com,
Anisa Su <anisa.su@samsung.com>
Subject: Re: [RESEND PATCH v13 8/8] Documentation/cxl: Document DPA partition layout and ordering rules
Date: Tue, 8 Sep 2026 23:17:00 +0100 [thread overview]
Message-ID: <20260908231700.1a8d53ec@jic23-huawei> (raw)
In-Reply-To: <20260908102124.2231730-10-anisa.su@samsung.com>
On Tue, 8 Sep 2026 03:15:12 -0700
Anisa Su <anisa.su887@gmail.com> wrote:
> DC Partitions complicate DPA ordering. Add a DPA Partitions section to
> cxl-driver.rst describing spec-mandated and Linux requirements for the
> layout.
>
> Suggested-by: Gregory Price <gourry@gourry.net>
> Signed-off-by: Anisa Su <anisa.su@samsung.com>
A couple of minor potential tweaks. Otherwise LGTM
Reviewed-by: Jonathan Cameron <jonathan.cameron@oss.qualcomm.com>
>
> ---
> New patch in v13.
> ---
> .../driver-api/cxl/linux/cxl-driver.rst | 38 +++++++++++++++++++
> 1 file changed, 38 insertions(+)
>
> diff --git a/Documentation/driver-api/cxl/linux/cxl-driver.rst b/Documentation/driver-api/cxl/linux/cxl-driver.rst
> index dd6dd17dc536..f0742d6c86c3 100644
> --- a/Documentation/driver-api/cxl/linux/cxl-driver.rst
> +++ b/Documentation/driver-api/cxl/linux/cxl-driver.rst
> @@ -181,6 +181,44 @@ A Memory Device is a discrete base object that is not a port. While the
> physical device it belongs to may also host an `endpoint`, the relationship
> between an `endpoint` and a `memdev` is not captured in sysfs.
>
> +DPA Partitions
> +~~~~~~~~~~~~~~
> +A memory device presents its capacity as one flat `Device Physical Address`
> +(DPA) space divided into `partitions`, which Linux lays out in a fixed
> +order::
> +
> + DPA 0 end
> + +---------------+---------------+---------------------------+
> + | ram | pmem | dynamic_ram_1 |
> + +---------------+---------------+---------------------------+
> + part[0] part[1] part[2]
> +
> +Part of that order is required by the CXL specification and part of it is a
> +Linux choice.
> +
> +The `ram` and `pmem` order is mandated. CXL r4.0 section 8.2.10.9.2.1 "Get
> +Partition Info" (4100h), Table 8-310, mandates that volatile capacity starts
> +at DPA 0 and pmem starts at the DPA immediately following it.
> +
> +Dynamic Capacity partitions only need to be 256MB aligned according to
> +CXL r4.0 section 8.2.10.9.9.1 "Get Dynamic Capacity Configuration"
> +(opcode 4800h), Table 8-347. So a device could leave a gap between ram/pmem
> +(static) capacity and its first DC partition, or between one DC partition
> +and the next.
> +
> +Linux follows the static precedent anyway for the partition it maps: the
Maybe "Linux chooses to only support...
> +first DC partition must begin at the DPA immediately following static
> +capacity -- after pmem, after ram on a device with no pmem, or at DPA 0 on
> +a device with no static capacity at all.
> +
> +Currently, only one dynamic partition is supported. A device may report up
> +to eight (CXL r4.0 Table 8-346); Linux configures the first and exposes it as
> +`dynamic_ram_1`.
> +
> +Support for additional dynamic partitions may be added if devices appear
> +that need it, which is what the `dynamic_ram_1` name leaves room for. Until
> +then a device offering more than one is still usable, just not in full.
I'd drop this last paragraph. Predicting the future is tricky, even with a may.
Hopefully anyone realises that if something is needed Linux doesn't support
they should propose patches to add it!
Jonathan
> +
> Port Relationships
> ~~~~~~~~~~~~~~~~~~
> In our example described above, there are four host bridges attached to the
next prev parent reply other threads:[~2026-09-08 22:17 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-08 10:15 [RESEND PATCH v13 0/8] DCD Prep Series Anisa Su
2026-09-08 10:15 ` [RESEND PATCH v13 1/8] cxl/mbox: Flag support for Dynamic Capacity Devices (DCD) Anisa Su
2026-09-08 15:39 ` dave
2026-09-08 18:45 ` Jonathan Cameron
2026-09-08 10:15 ` [RESEND PATCH v13 2/8] cxl/mem: Read dynamic capacity configuration from the device Anisa Su
2026-09-08 15:59 ` Davidlohr Bueso
2026-09-08 20:43 ` Jonathan Cameron
2026-09-10 23:56 ` Anisa Su
2026-09-11 0:53 ` Jonathan Cameron
2026-09-11 16:38 ` Anisa Su
2026-09-08 10:15 ` [RESEND PATCH v13 3/8] cxl/cdat: Gather DSMAS data for DCD partitions Anisa Su
2026-09-08 20:52 ` Jonathan Cameron
2026-09-11 0:02 ` Anisa Su
2026-09-11 0:56 ` Jonathan Cameron
2026-09-11 16:37 ` Anisa Su
2026-09-08 10:15 ` [RESEND PATCH v13 4/8] cxl/events: Split event msgnum configuration from irq setup Anisa Su
2026-09-08 16:37 ` Davidlohr Bueso
2026-09-08 10:15 ` [RESEND PATCH v13 5/8] cxl/pci: Factor out interrupt policy check Anisa Su
2026-09-08 17:17 ` Davidlohr Bueso
2026-09-08 10:15 ` [RESEND PATCH v13 6/8] cxl/mem: Configure dynamic capacity interrupts Anisa Su
2026-09-08 10:43 ` sashiko-bot
2026-09-11 21:10 ` Anisa Su
2026-09-12 0:09 ` Gregory Price
2026-09-08 22:14 ` Jonathan Cameron
2026-09-11 18:21 ` Anisa Su
2026-09-08 10:15 ` [RESEND PATCH v13 7/8] cxl/core: Enforce partition order/simplify partition calls Anisa Su
2026-09-08 10:15 ` [RESEND PATCH v13 8/8] Documentation/cxl: Document DPA partition layout and ordering rules Anisa Su
2026-09-08 22:17 ` Jonathan Cameron [this message]
2026-09-11 20:39 ` Anisa Su
2026-09-09 15:19 ` Davidlohr Bueso
2026-09-11 20:38 ` Anisa Su
2026-09-11 20:50 ` Davidlohr Bueso
2026-09-12 0:20 ` Gregory Price
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