From: Junjie Cao <junjie.cao@intel.com>
To: Manish Honap <mhonap@nvidia.com>
Cc: alex@shazbot.org, ankita@nvidia.com, jic23@kernel.org,
dave.jiang@intel.com, alejandro.lucero-palau@amd.com,
smadhavan@nvidia.com, pierrick.bouvier@oss.qualcomm.com,
mst@redhat.com, imammedo@redhat.com, anisinha@redhat.com,
pbonzini@redhat.com, eric.auger@redhat.com,
peter.maydell@linaro.org, richard.henderson@linaro.org,
clg@redhat.com, cohuck@redhat.com, kjaju@nvidia.com,
vsethi@nvidia.com, zhiw@nvidia.com, qemu-devel@nongnu.org,
qemu-arm@nongnu.org, linux-cxl@vger.kernel.org
Subject: Re: [PATCH v2 07/10] hw/vfio/pci: Map the CXL memory on the guest decoder commit
Date: Sun, 20 Sep 2026 17:14:03 +0800 [thread overview]
Message-ID: <20260920091403.716987-1-junjie.cao@intel.com> (raw)
In-Reply-To: <20260916184412.3825713-8-mhonap@nvidia.com>
On Thu, 17 Sep 2026 00:14:09 +0530, Manish Honap wrote:
> + * Record the base the guest programs into a decoder so the commit handler
> + * can reject a base other than the device's CFMWS window. The base low
[...]
> + vdev->cxl.guest_base_lo = (uint32_t)data & VFIO_CXL_HDM_BASE_LOW_MASK;
> + vdev->cxl.guest_base_written = true;
This answered my v1 question for the kernel v4 FSM model. With v5
(20/27) the kernel gives a live read-only view and leaves any write
virtualization to the VMM, and what QEMU shows the guest is a
committed, locked decoder at the window base. A locked decoder
ignores a base write, but here it is recorded, and if it differs from
the window base the next rescan unmaps while reads still return
Committed at the window base. That is the mismatch the check was
meant to prevent. A current Linux guest never writes a locked
decoder, so it won't trip this.
Is the guest-written base still meant to matter in this model? If
not, guest_base_{lo,hi,written} can go.
> + * The kernel runs the lock-on-commit FSM in the write above, so the
> + * committed state is settled by now; a control write on any decoder can
Stale now that the kernel no longer acts on the write?
Junjie
next prev parent reply other threads:[~2026-09-20 9:14 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-16 18:44 [PATCH v2 00/10] QEMU: CXL Type-2 device passthrough via vfio-pci mhonap
2026-09-16 18:44 ` [PATCH v2 01/10] linux-headers: Update vfio.h for CXL Type-2 passthrough mhonap
2026-09-16 18:44 ` [PATCH v2 02/10] hw/vfio/region: Add vfio_region_setup_with_ops() mhonap
2026-09-17 13:27 ` Cédric Le Goater
2026-09-21 10:48 ` Manish Honap
2026-09-16 18:44 ` [PATCH v2 03/10] hw/vfio/pci: Detect a CXL Type-2 device and read its geometry mhonap
2026-09-17 16:04 ` Cédric Le Goater
2026-09-21 10:49 ` Manish Honap
2026-09-16 18:44 ` [PATCH v2 04/10] hw/vfio/pci: Enforce the passthrough topology for a CXL device mhonap
2026-09-17 13:20 ` Cédric Le Goater
2026-09-21 10:45 ` Manish Honap
2026-09-16 18:44 ` [PATCH v2 05/10] hw/vfio/pci: Back the CXL memory with a RAM-device region mhonap
2026-09-17 13:56 ` Cédric Le Goater
2026-09-21 10:55 ` Manish Honap
2026-09-16 18:44 ` [PATCH v2 06/10] hw/vfio/pci: Bind a CXL device to its fixed memory window mhonap
2026-09-17 16:00 ` Cédric Le Goater
2026-09-21 11:03 ` Manish Honap
2026-09-16 18:44 ` [PATCH v2 07/10] hw/vfio/pci: Map the CXL memory on the guest decoder commit mhonap
2026-09-18 16:08 ` Cédric Le Goater
2026-09-21 11:14 ` Manish Honap
2026-09-20 9:14 ` Junjie Cao [this message]
2026-09-21 11:17 ` Manish Honap
2026-09-16 18:44 ` [PATCH v2 08/10] docs/cxl: Document CXL Type-2 device passthrough mhonap
2026-09-16 18:44 ` [PATCH v2 09/10] hw/arm/smmu-common: Allow pxb-cxl as an SMMUv3 primary bus mhonap
2026-09-16 18:44 ` [PATCH v2 10/10] hw/pci-host: Emit a _DSM on pxb-cxl to preserve firmware PCI config mhonap
2026-09-20 9:14 ` Junjie Cao
2026-09-21 11:20 ` Manish Honap
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