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From: <mhonap@nvidia.com>
To: <alex@shazbot.org>, <ankita@nvidia.com>, <jic23@kernel.org>,
	<dave.jiang@intel.com>, <alejandro.lucero-palau@amd.com>,
	<smadhavan@nvidia.com>, <pierrick.bouvier@oss.qualcomm.com>,
	<mst@redhat.com>, <imammedo@redhat.com>, <anisinha@redhat.com>,
	<pbonzini@redhat.com>, <eric.auger@redhat.com>,
	<peter.maydell@linaro.org>, <richard.henderson@linaro.org>,
	<clg@redhat.com>, <cohuck@redhat.com>
Cc: <kjaju@nvidia.com>, <vsethi@nvidia.com>, <zhiw@nvidia.com>,
	<mhonap@nvidia.com>, <qemu-devel@nongnu.org>,
	<qemu-arm@nongnu.org>, <linux-cxl@vger.kernel.org>,
	Shameer Kolothum <skolothumtho@nvidia.com>
Subject: [PATCH v2 09/10] hw/arm/smmu-common: Allow pxb-cxl as an SMMUv3 primary bus
Date: Thu, 17 Sep 2026 00:14:11 +0530	[thread overview]
Message-ID: <20260916184412.3825713-10-mhonap@nvidia.com> (raw)
In-Reply-To: <20260916184412.3825713-1-mhonap@nvidia.com>

From: Manish Honap <mhonap@nvidia.com>

The SMMUv3 primary-bus check only accepted pxb-pcie as a valid extra
root complex, so a CXL device behind a pxb-cxl could not reach the
IOMMU: attaching an arm-smmuv3 to a pxb-cxl bus failed at realize with
"SMMU should be attached to a default PCIe root complex (pcie.0) or a
pxb-pcie based root complex".

A pxb-cxl uses the same PCIe-compatible bus as a pxb-pcie, so accept it
too. A CXL Type-2 device passed through with vfio-pci sits behind a
pxb-cxl and needs SMMU translation for its DMA and ATS just like a
pxb-pcie device.

AI-used-for: code (prototype)
Signed-off-by: Shameer Kolothum <skolothumtho@nvidia.com>
Signed-off-by: Manish Honap <mhonap@nvidia.com>
---
 hw/arm/smmu-common.c | 19 ++++++++++---------
 1 file changed, 10 insertions(+), 9 deletions(-)

diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c
index 8e40ba603d..42fb098ab2 100644
--- a/hw/arm/smmu-common.c
+++ b/hw/arm/smmu-common.c
@@ -963,19 +963,20 @@ static void smmu_base_realize(DeviceState *dev, Error **errp)
         s->iommu_ops = &smmu_ops;
     }
     /*
-     * We only allow default PCIe Root Complex(pcie.0) or pxb-pcie based extra
-     * root complexes to be associated with SMMU.
+     * We only allow the default PCIe root complex (pcie.0) or pxb-pcie /
+     * pxb-cxl based extra root complexes to be associated with SMMU.
      */
     if (pci_bus_is_express(pci_bus) && pci_bus_is_root(pci_bus) &&
         object_dynamic_cast(OBJECT(pci_bus)->parent, TYPE_PCI_HOST_BRIDGE)) {
         /*
-         * This condition matches either the default pcie.0, pxb-pcie, or
-         * pxb-cxl. For both pxb-pcie and pxb-cxl, parent_dev will be set.
-         * Currently, we don't allow pxb-cxl as it requires further
-         * verification. Therefore, make sure this is indeed pxb-pcie.
+         * pcie.0 has no parent_dev; pxb-pcie and pxb-cxl do. Accept both bus
+         * types explicitly so other root complexes are still rejected. A
+         * pxb-cxl uses the same PCIe-compatible bus, so a CXL device behind it
+         * needs the SMMU just like a pxb-pcie one.
          */
         if (pci_bus->parent_dev) {
-            if (!object_dynamic_cast(OBJECT(pci_bus), TYPE_PXB_PCIE_BUS)) {
+            if (!object_dynamic_cast(OBJECT(pci_bus), TYPE_PXB_PCIE_BUS) &&
+                !object_dynamic_cast(OBJECT(pci_bus), TYPE_PXB_CXL_BUS)) {
                 goto out_err;
             }
         }
@@ -990,8 +991,8 @@ static void smmu_base_realize(DeviceState *dev, Error **errp)
         return;
     }
 out_err:
-    error_setg(errp, "SMMU should be attached to a default PCIe root complex"
-               "(pcie.0) or a pxb-pcie based root complex");
+    error_setg(errp, "SMMU should be attached to a default PCIe root complex "
+               "(pcie.0), a pxb-pcie, or a pxb-cxl based root complex");
 }
 
 /*
-- 
2.25.1


  parent reply	other threads:[~2026-09-16 18:46 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-09-16 18:44 [PATCH v2 00/10] QEMU: CXL Type-2 device passthrough via vfio-pci mhonap
2026-09-16 18:44 ` [PATCH v2 01/10] linux-headers: Update vfio.h for CXL Type-2 passthrough mhonap
2026-09-16 18:44 ` [PATCH v2 02/10] hw/vfio/region: Add vfio_region_setup_with_ops() mhonap
2026-09-17 13:27   ` Cédric Le Goater
2026-09-21 10:48     ` Manish Honap
2026-09-16 18:44 ` [PATCH v2 03/10] hw/vfio/pci: Detect a CXL Type-2 device and read its geometry mhonap
2026-09-17 16:04   ` Cédric Le Goater
2026-09-21 10:49     ` Manish Honap
2026-09-16 18:44 ` [PATCH v2 04/10] hw/vfio/pci: Enforce the passthrough topology for a CXL device mhonap
2026-09-17 13:20   ` Cédric Le Goater
2026-09-21 10:45     ` Manish Honap
2026-09-16 18:44 ` [PATCH v2 05/10] hw/vfio/pci: Back the CXL memory with a RAM-device region mhonap
2026-09-17 13:56   ` Cédric Le Goater
2026-09-21 10:55     ` Manish Honap
2026-09-16 18:44 ` [PATCH v2 06/10] hw/vfio/pci: Bind a CXL device to its fixed memory window mhonap
2026-09-17 16:00   ` Cédric Le Goater
2026-09-21 11:03     ` Manish Honap
2026-09-16 18:44 ` [PATCH v2 07/10] hw/vfio/pci: Map the CXL memory on the guest decoder commit mhonap
2026-09-18 16:08   ` Cédric Le Goater
2026-09-21 11:14     ` Manish Honap
2026-09-20  9:14   ` Junjie Cao
2026-09-21 11:17     ` Manish Honap
2026-09-16 18:44 ` [PATCH v2 08/10] docs/cxl: Document CXL Type-2 device passthrough mhonap
2026-09-16 18:44 ` mhonap [this message]
2026-09-16 18:44 ` [PATCH v2 10/10] hw/pci-host: Emit a _DSM on pxb-cxl to preserve firmware PCI config mhonap
2026-09-20  9:14   ` Junjie Cao
2026-09-21 11:20     ` Manish Honap

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