From: Dave Jiang <dave.jiang@intel.com>
To: alejandro.lucero-palau@amd.com, linux-cxl@vger.kernel.org,
netdev@vger.kernel.org, dan.j.williams@intel.com,
edward.cree@amd.com, davem@davemloft.net, kuba@kernel.org,
pabeni@redhat.com, edumazet@google.com
Cc: Alejandro Lucero <alucerop@amd.com>,
Jonathan Cameron <Jonathan.Cameron@huawei.com>,
Edward Cree <ecree.xilinx@gmail.com>,
Alison Schofield <alison.schofield@intel.com>
Subject: Re: [PATCH v18 02/20] sfc: add cxl support
Date: Thu, 18 Sep 2025 16:25:00 -0700 [thread overview]
Message-ID: <276c41a7-f61c-4f9e-8cf1-4a458c3fe9bd@intel.com> (raw)
In-Reply-To: <20250918091746.2034285-3-alejandro.lucero-palau@amd.com>
On 9/18/25 2:17 AM, alejandro.lucero-palau@amd.com wrote:
> From: Alejandro Lucero <alucerop@amd.com>
>
> Add CXL initialization based on new CXL API for accel drivers and make
> it dependent on kernel CXL configuration.
>
> Signed-off-by: Alejandro Lucero <alucerop@amd.com>
> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> Acked-by: Edward Cree <ecree.xilinx@gmail.com>
> Reviewed-by: Alison Schofield <alison.schofield@intel.com>
> Reviewed-by: Dan Williams <dan.j.williams@intel.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
> ---
> drivers/net/ethernet/sfc/Kconfig | 9 +++++
> drivers/net/ethernet/sfc/Makefile | 1 +
> drivers/net/ethernet/sfc/efx.c | 15 ++++++-
> drivers/net/ethernet/sfc/efx_cxl.c | 57 +++++++++++++++++++++++++++
> drivers/net/ethernet/sfc/efx_cxl.h | 40 +++++++++++++++++++
> drivers/net/ethernet/sfc/net_driver.h | 10 +++++
> 6 files changed, 131 insertions(+), 1 deletion(-)
> create mode 100644 drivers/net/ethernet/sfc/efx_cxl.c
> create mode 100644 drivers/net/ethernet/sfc/efx_cxl.h
>
> diff --git a/drivers/net/ethernet/sfc/Kconfig b/drivers/net/ethernet/sfc/Kconfig
> index c4c43434f314..979f2801e2a8 100644
> --- a/drivers/net/ethernet/sfc/Kconfig
> +++ b/drivers/net/ethernet/sfc/Kconfig
> @@ -66,6 +66,15 @@ config SFC_MCDI_LOGGING
> Driver-Interface) commands and responses, allowing debugging of
> driver/firmware interaction. The tracing is actually enabled by
> a sysfs file 'mcdi_logging' under the PCI device.
> +config SFC_CXL
> + bool "Solarflare SFC9100-family CXL support"
> + depends on SFC && CXL_BUS >= SFC
> + default SFC
> + help
> + This enables SFC CXL support if the kernel is configuring CXL for
> + using CTPIO with CXL.mem. The SFC device with CXL support and
> + with a CXL-aware firmware can be used for minimizing latencies
> + when sending through CTPIO.
>
> source "drivers/net/ethernet/sfc/falcon/Kconfig"
> source "drivers/net/ethernet/sfc/siena/Kconfig"
> diff --git a/drivers/net/ethernet/sfc/Makefile b/drivers/net/ethernet/sfc/Makefile
> index d99039ec468d..bb0f1891cde6 100644
> --- a/drivers/net/ethernet/sfc/Makefile
> +++ b/drivers/net/ethernet/sfc/Makefile
> @@ -13,6 +13,7 @@ sfc-$(CONFIG_SFC_SRIOV) += sriov.o ef10_sriov.o ef100_sriov.o ef100_rep.o \
> mae.o tc.o tc_bindings.o tc_counters.o \
> tc_encap_actions.o tc_conntrack.o
>
> +sfc-$(CONFIG_SFC_CXL) += efx_cxl.o
> obj-$(CONFIG_SFC) += sfc.o
>
> obj-$(CONFIG_SFC_FALCON) += falcon/
> diff --git a/drivers/net/ethernet/sfc/efx.c b/drivers/net/ethernet/sfc/efx.c
> index 112e55b98ed3..537668278375 100644
> --- a/drivers/net/ethernet/sfc/efx.c
> +++ b/drivers/net/ethernet/sfc/efx.c
> @@ -34,6 +34,7 @@
> #include "selftest.h"
> #include "sriov.h"
> #include "efx_devlink.h"
> +#include "efx_cxl.h"
>
> #include "mcdi_port_common.h"
> #include "mcdi_pcol.h"
> @@ -981,12 +982,15 @@ static void efx_pci_remove(struct pci_dev *pci_dev)
> efx_pci_remove_main(efx);
>
> efx_fini_io(efx);
> +
> + probe_data = container_of(efx, struct efx_probe_data, efx);
> + efx_cxl_exit(probe_data);
> +
> pci_dbg(efx->pci_dev, "shutdown successful\n");
>
> efx_fini_devlink_and_unlock(efx);
> efx_fini_struct(efx);
> free_netdev(efx->net_dev);
> - probe_data = container_of(efx, struct efx_probe_data, efx);
> kfree(probe_data);
> };
>
> @@ -1190,6 +1194,15 @@ static int efx_pci_probe(struct pci_dev *pci_dev,
> if (rc)
> goto fail2;
>
> + /* A successful cxl initialization implies a CXL region created to be
> + * used for PIO buffers. If there is no CXL support, or initialization
> + * fails, efx_cxl_pio_initialised will be false and legacy PIO buffers
> + * defined at specific PCI BAR regions will be used.
> + */
> + rc = efx_cxl_init(probe_data);
> + if (rc)
> + pci_err(pci_dev, "CXL initialization failed with error %d\n", rc);
> +
> rc = efx_pci_probe_post_io(efx);
> if (rc) {
> /* On failure, retry once immediately.
> diff --git a/drivers/net/ethernet/sfc/efx_cxl.c b/drivers/net/ethernet/sfc/efx_cxl.c
> new file mode 100644
> index 000000000000..56d148318636
> --- /dev/null
> +++ b/drivers/net/ethernet/sfc/efx_cxl.c
> @@ -0,0 +1,57 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/****************************************************************************
> + *
> + * Driver for AMD network controllers and boards
> + * Copyright (C) 2025, Advanced Micro Devices, Inc.
> + */
> +
> +#include <cxl/pci.h>
> +#include <linux/pci.h>
> +
> +#include "net_driver.h"
> +#include "efx_cxl.h"
> +
> +#define EFX_CTPIO_BUFFER_SIZE SZ_256M
> +
> +int efx_cxl_init(struct efx_probe_data *probe_data)
> +{
> + struct efx_nic *efx = &probe_data->efx;
> + struct pci_dev *pci_dev = efx->pci_dev;
> + struct efx_cxl *cxl;
> + u16 dvsec;
> +
> + probe_data->cxl_pio_initialised = false;
> +
> + /* Is the device configured with and using CXL? */
> + if (!pcie_is_cxl(pci_dev))
> + return 0;
> +
> + dvsec = pci_find_dvsec_capability(pci_dev, PCI_VENDOR_ID_CXL,
> + CXL_DVSEC_PCIE_DEVICE);
> + if (!dvsec) {
> + pci_err(pci_dev, "CXL_DVSEC_PCIE_DEVICE capability not found\n");
> + return 0;
> + }
> +
> + pci_dbg(pci_dev, "CXL_DVSEC_PCIE_DEVICE capability found\n");
> +
> + /* Create a cxl_dev_state embedded in the cxl struct using cxl core api
> + * specifying no mbox available.
> + */
> + cxl = devm_cxl_dev_state_create(&pci_dev->dev, CXL_DEVTYPE_DEVMEM,
> + pci_dev->dev.id, dvsec, struct efx_cxl,
> + cxlds, false);
> +
> + if (!cxl)
> + return -ENOMEM;
> +
> + probe_data->cxl = cxl;
> +
> + return 0;
> +}
> +
> +void efx_cxl_exit(struct efx_probe_data *probe_data)
> +{
> +}
> +
> +MODULE_IMPORT_NS("CXL");
> diff --git a/drivers/net/ethernet/sfc/efx_cxl.h b/drivers/net/ethernet/sfc/efx_cxl.h
> new file mode 100644
> index 000000000000..961639cef692
> --- /dev/null
> +++ b/drivers/net/ethernet/sfc/efx_cxl.h
> @@ -0,0 +1,40 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/****************************************************************************
> + * Driver for AMD network controllers and boards
> + * Copyright (C) 2025, Advanced Micro Devices, Inc.
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License version 2 as published
> + * by the Free Software Foundation, incorporated herein by reference.
> + */
> +
> +#ifndef EFX_CXL_H
> +#define EFX_CXL_H
> +
> +#ifdef CONFIG_SFC_CXL
> +
> +#include <cxl/cxl.h>
> +
> +struct cxl_root_decoder;
> +struct cxl_port;
> +struct cxl_endpoint_decoder;
> +struct cxl_region;
> +struct efx_probe_data;
> +
> +struct efx_cxl {
> + struct cxl_dev_state cxlds;
> + struct cxl_memdev *cxlmd;
> + struct cxl_root_decoder *cxlrd;
> + struct cxl_port *endpoint;
> + struct cxl_endpoint_decoder *cxled;
> + struct cxl_region *efx_region;
> + void __iomem *ctpio_cxl;
> +};
> +
> +int efx_cxl_init(struct efx_probe_data *probe_data);
> +void efx_cxl_exit(struct efx_probe_data *probe_data);
> +#else
> +static inline int efx_cxl_init(struct efx_probe_data *probe_data) { return 0; }
> +static inline void efx_cxl_exit(struct efx_probe_data *probe_data) {}
> +#endif
> +#endif
> diff --git a/drivers/net/ethernet/sfc/net_driver.h b/drivers/net/ethernet/sfc/net_driver.h
> index 5c0f306fb019..0e685b8a9980 100644
> --- a/drivers/net/ethernet/sfc/net_driver.h
> +++ b/drivers/net/ethernet/sfc/net_driver.h
> @@ -1199,14 +1199,24 @@ struct efx_nic {
> atomic_t n_rx_noskb_drops;
> };
>
> +#ifdef CONFIG_SFC_CXL
> +struct efx_cxl;
> +#endif
> +
> /**
> * struct efx_probe_data - State after hardware probe
> * @pci_dev: The PCI device
> * @efx: Efx NIC details
> + * @cxl: details of related cxl objects
> + * @cxl_pio_initialised: cxl initialization outcome.
> */
> struct efx_probe_data {
> struct pci_dev *pci_dev;
> struct efx_nic efx;
> +#ifdef CONFIG_SFC_CXL
> + struct efx_cxl *cxl;
> + bool cxl_pio_initialised;
> +#endif
> };
>
> static inline struct efx_nic *efx_netdev_priv(struct net_device *dev)
next prev parent reply other threads:[~2025-09-18 23:25 UTC|newest]
Thread overview: 88+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-18 9:17 [PATCH v18 00/20] Type2 device basic support alejandro.lucero-palau
2025-09-18 9:17 ` [PATCH v18 01/20] cxl: Add type2 " alejandro.lucero-palau
2025-09-18 10:55 ` Jonathan Cameron
2025-09-23 11:21 ` Alejandro Lucero Palau
2025-09-29 10:21 ` Alejandro Lucero Palau
2025-09-30 14:43 ` Jonathan Cameron
2025-09-22 21:08 ` Cheatham, Benjamin
2025-09-23 11:43 ` Alejandro Lucero Palau
2025-09-18 9:17 ` [PATCH v18 02/20] sfc: add cxl support alejandro.lucero-palau
2025-09-18 23:25 ` Dave Jiang [this message]
2025-09-18 9:17 ` [PATCH v18 03/20] cxl: Move pci generic code alejandro.lucero-palau
2025-09-22 21:10 ` Cheatham, Benjamin
2025-09-25 9:27 ` Alejandro Lucero Palau
2025-09-18 9:17 ` [PATCH v18 04/20] cxl: allow Type2 drivers to map cxl component regs alejandro.lucero-palau
2025-09-18 11:03 ` Jonathan Cameron
2025-09-24 8:25 ` Alejandro Lucero Palau
2025-09-25 8:53 ` Alejandro Lucero Palau
2025-09-18 23:30 ` Dave Jiang
2025-09-22 21:08 ` Cheatham, Benjamin
2025-09-24 8:36 ` Alejandro Lucero Palau
2025-10-01 23:20 ` PJ Waskiewicz
2025-10-02 9:36 ` Alejandro Lucero Palau
2025-10-07 21:23 ` PJ Waskiewicz
2025-09-18 9:17 ` [PATCH v18 05/20] cxl: Support dpa initialization without a mailbox alejandro.lucero-palau
2025-09-18 23:38 ` Dave Jiang
2025-09-22 21:09 ` Cheatham, Benjamin
2025-09-18 9:17 ` [PATCH v18 06/20] cxl: Prepare memdev creation for type2 alejandro.lucero-palau
2025-09-22 21:10 ` Cheatham, Benjamin
2025-09-24 8:44 ` Alejandro Lucero Palau
2025-09-18 9:17 ` [PATCH v18 07/20] sfc: create type2 cxl memdev alejandro.lucero-palau
2025-09-18 11:08 ` Jonathan Cameron
2025-09-19 15:59 ` Dave Jiang
2025-09-19 19:58 ` Dave Jiang
2025-09-24 8:56 ` Alejandro Lucero Palau
2025-09-18 9:17 ` [PATCH v18 08/20] cx/memdev: Indicate probe deferral alejandro.lucero-palau
2025-09-18 11:19 ` Jonathan Cameron
2025-09-19 17:53 ` Dave Jiang
2025-09-24 16:11 ` Alejandro Lucero Palau
2025-09-18 9:17 ` [PATCH v18 09/20] cxl: Define a driver interface for HPA free space enumeration alejandro.lucero-palau
2025-09-18 14:35 ` Jonathan Cameron
2025-09-24 16:16 ` Alejandro Lucero Palau
2025-09-30 14:47 ` Jonathan Cameron
2025-09-22 21:09 ` Cheatham, Benjamin
2025-09-24 16:53 ` Alejandro Lucero Palau
2025-09-18 9:17 ` [PATCH v18 10/20] sfc: get root decoder alejandro.lucero-palau
2025-09-19 18:20 ` Dave Jiang
2025-09-22 21:09 ` Cheatham, Benjamin
2025-09-18 9:17 ` [PATCH v18 11/20] cxl: Define a driver interface for DPA allocation alejandro.lucero-palau
2025-09-18 14:52 ` Jonathan Cameron
2025-09-25 9:18 ` Alejandro Lucero Palau
2025-09-19 19:46 ` Dave Jiang
2025-09-25 9:21 ` Alejandro Lucero Palau
2025-09-22 21:09 ` Cheatham, Benjamin
2025-09-25 9:25 ` Alejandro Lucero Palau
2025-09-18 9:17 ` [PATCH v18 12/20] sfc: get endpoint decoder alejandro.lucero-palau
2025-09-18 14:53 ` Jonathan Cameron
2025-09-25 9:45 ` Alejandro Lucero Palau
2025-09-22 21:09 ` Cheatham, Benjamin
2025-09-25 9:48 ` Alejandro Lucero Palau
2025-09-18 9:17 ` [PATCH v18 13/20] cxl: Make region type based on endpoint type alejandro.lucero-palau
2025-09-18 9:17 ` [PATCH v18 14/20] cxl/region: Factor out interleave ways setup alejandro.lucero-palau
2025-09-18 9:17 ` [PATCH v18 15/20] cxl/region: Factor out interleave granularity setup alejandro.lucero-palau
2025-09-18 9:17 ` [PATCH v18 16/20] cxl: Allow region creation by type2 drivers alejandro.lucero-palau
2025-09-18 14:58 ` Jonathan Cameron
2025-09-19 20:59 ` Dave Jiang
2025-09-26 8:59 ` Alejandro Lucero Palau
2025-09-30 0:52 ` Dave Jiang
2025-10-06 7:12 ` Alejandro Lucero Palau
2025-09-22 21:09 ` Cheatham, Benjamin
2025-09-26 9:01 ` Alejandro Lucero Palau
2025-09-18 9:17 ` [PATCH v18 17/20] cxl: Avoid dax creation for accelerators alejandro.lucero-palau
2025-09-19 21:16 ` Dave Jiang
2025-09-22 21:09 ` Cheatham, Benjamin
2025-09-18 9:17 ` [PATCH v18 18/20] sfc: create cxl region alejandro.lucero-palau
2025-09-18 15:03 ` Jonathan Cameron
2025-09-26 9:27 ` Alejandro Lucero Palau
2025-09-18 9:17 ` [PATCH v18 19/20] cxl: Add function for obtaining region range alejandro.lucero-palau
2025-09-18 9:17 ` [PATCH v18 20/20] sfc: support pio mapping based on cxl alejandro.lucero-palau
2025-09-18 15:08 ` Jonathan Cameron
2025-09-26 9:47 ` Alejandro Lucero Palau
2025-09-30 14:51 ` Jonathan Cameron
2025-09-19 12:51 ` [PATCH v18 00/20] Type2 device basic support Alejandro Lucero Palau
2025-09-19 16:26 ` Dave Jiang
2025-09-19 16:55 ` Alejandro Lucero Palau
2025-09-19 21:42 ` Dave Jiang
2025-09-23 10:35 ` Alejandro Lucero Palau
2025-09-23 18:28 ` Dave Jiang
2025-09-22 21:10 ` Cheatham, Benjamin
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