From: Dave Jiang <dave.jiang@intel.com>
To: alejandro.lucero-palau@amd.com, linux-cxl@vger.kernel.org,
netdev@vger.kernel.org, dan.j.williams@intel.com,
edward.cree@amd.com, davem@davemloft.net, kuba@kernel.org,
pabeni@redhat.com, edumazet@google.com
Cc: Alejandro Lucero <alucerop@amd.com>
Subject: Re: [PATCH v18 05/20] cxl: Support dpa initialization without a mailbox
Date: Thu, 18 Sep 2025 16:38:24 -0700 [thread overview]
Message-ID: <b6b145e5-d3be-4eb1-b280-c2b7f2274c7d@intel.com> (raw)
In-Reply-To: <20250918091746.2034285-6-alejandro.lucero-palau@amd.com>
On 9/18/25 2:17 AM, alejandro.lucero-palau@amd.com wrote:
> From: Alejandro Lucero <alucerop@amd.com>
>
> Type3 relies on mailbox CXL_MBOX_OP_IDENTIFY command for initializing
> memdev state params which end up being used for DPA initialization.
>
> Allow a Type2 driver to initialize DPA simply by giving the size of its
> volatile hardware partition.
>
> Move related functions to memdev.
>
> Add sfc driver as the client.
>
> Signed-off-by: Alejandro Lucero <alucerop@amd.com>
> Reviewed-by: Dan Williams <dan.j.williams@intel.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
> ---
> drivers/cxl/core/core.h | 2 +
> drivers/cxl/core/mbox.c | 51 +----------------------
> drivers/cxl/core/memdev.c | 66 ++++++++++++++++++++++++++++++
> drivers/net/ethernet/sfc/efx_cxl.c | 4 ++
> include/cxl/cxl.h | 1 +
> 5 files changed, 74 insertions(+), 50 deletions(-)
>
> diff --git a/drivers/cxl/core/core.h b/drivers/cxl/core/core.h
> index d96213c02fd6..c4dddbec5d6e 100644
> --- a/drivers/cxl/core/core.h
> +++ b/drivers/cxl/core/core.h
> @@ -90,6 +90,8 @@ void __iomem *devm_cxl_iomap_block(struct device *dev, resource_size_t addr,
> struct dentry *cxl_debugfs_create_dir(const char *dir);
> int cxl_dpa_set_part(struct cxl_endpoint_decoder *cxled,
> enum cxl_partition_mode mode);
> +struct cxl_memdev_state;
> +int cxl_mem_get_partition_info(struct cxl_memdev_state *mds);
> int cxl_dpa_alloc(struct cxl_endpoint_decoder *cxled, u64 size);
> int cxl_dpa_free(struct cxl_endpoint_decoder *cxled);
> resource_size_t cxl_dpa_size(struct cxl_endpoint_decoder *cxled);
> diff --git a/drivers/cxl/core/mbox.c b/drivers/cxl/core/mbox.c
> index bee84d0101d1..d57a0c2d39fb 100644
> --- a/drivers/cxl/core/mbox.c
> +++ b/drivers/cxl/core/mbox.c
> @@ -1144,7 +1144,7 @@ EXPORT_SYMBOL_NS_GPL(cxl_mem_get_event_records, "CXL");
> *
> * See CXL @8.2.9.5.2.1 Get Partition Info
> */
> -static int cxl_mem_get_partition_info(struct cxl_memdev_state *mds)
> +int cxl_mem_get_partition_info(struct cxl_memdev_state *mds)
> {
> struct cxl_mailbox *cxl_mbox = &mds->cxlds.cxl_mbox;
> struct cxl_mbox_get_partition_info pi;
> @@ -1300,55 +1300,6 @@ int cxl_mem_sanitize(struct cxl_memdev *cxlmd, u16 cmd)
> return -EBUSY;
> }
>
> -static void add_part(struct cxl_dpa_info *info, u64 start, u64 size, enum cxl_partition_mode mode)
> -{
> - int i = info->nr_partitions;
> -
> - if (size == 0)
> - return;
> -
> - info->part[i].range = (struct range) {
> - .start = start,
> - .end = start + size - 1,
> - };
> - info->part[i].mode = mode;
> - info->nr_partitions++;
> -}
> -
> -int cxl_mem_dpa_fetch(struct cxl_memdev_state *mds, struct cxl_dpa_info *info)
> -{
> - struct cxl_dev_state *cxlds = &mds->cxlds;
> - struct device *dev = cxlds->dev;
> - int rc;
> -
> - if (!cxlds->media_ready) {
> - info->size = 0;
> - return 0;
> - }
> -
> - info->size = mds->total_bytes;
> -
> - if (mds->partition_align_bytes == 0) {
> - add_part(info, 0, mds->volatile_only_bytes, CXL_PARTMODE_RAM);
> - add_part(info, mds->volatile_only_bytes,
> - mds->persistent_only_bytes, CXL_PARTMODE_PMEM);
> - return 0;
> - }
> -
> - rc = cxl_mem_get_partition_info(mds);
> - if (rc) {
> - dev_err(dev, "Failed to query partition information\n");
> - return rc;
> - }
> -
> - add_part(info, 0, mds->active_volatile_bytes, CXL_PARTMODE_RAM);
> - add_part(info, mds->active_volatile_bytes, mds->active_persistent_bytes,
> - CXL_PARTMODE_PMEM);
> -
> - return 0;
> -}
> -EXPORT_SYMBOL_NS_GPL(cxl_mem_dpa_fetch, "CXL");
> -
> int cxl_get_dirty_count(struct cxl_memdev_state *mds, u32 *count)
> {
> struct cxl_mailbox *cxl_mbox = &mds->cxlds.cxl_mbox;
> diff --git a/drivers/cxl/core/memdev.c b/drivers/cxl/core/memdev.c
> index 97127d6067c4..d148a0c942aa 100644
> --- a/drivers/cxl/core/memdev.c
> +++ b/drivers/cxl/core/memdev.c
> @@ -556,6 +556,72 @@ bool is_cxl_memdev(const struct device *dev)
> }
> EXPORT_SYMBOL_NS_GPL(is_cxl_memdev, "CXL");
>
> +static void add_part(struct cxl_dpa_info *info, u64 start, u64 size, enum cxl_partition_mode mode)
> +{
> + int i = info->nr_partitions;
> +
> + if (size == 0)
> + return;
> +
> + info->part[i].range = (struct range) {
> + .start = start,
> + .end = start + size - 1,
> + };
> + info->part[i].mode = mode;
> + info->nr_partitions++;
> +}
> +
> +int cxl_mem_dpa_fetch(struct cxl_memdev_state *mds, struct cxl_dpa_info *info)
> +{
> + struct cxl_dev_state *cxlds = &mds->cxlds;
> + struct device *dev = cxlds->dev;
> + int rc;
> +
> + if (!cxlds->media_ready) {
> + info->size = 0;
> + return 0;
> + }
> +
> + info->size = mds->total_bytes;
> +
> + if (mds->partition_align_bytes == 0) {
> + add_part(info, 0, mds->volatile_only_bytes, CXL_PARTMODE_RAM);
> + add_part(info, mds->volatile_only_bytes,
> + mds->persistent_only_bytes, CXL_PARTMODE_PMEM);
> + return 0;
> + }
> +
> + rc = cxl_mem_get_partition_info(mds);
> + if (rc) {
> + dev_err(dev, "Failed to query partition information\n");
> + return rc;
> + }
> +
> + add_part(info, 0, mds->active_volatile_bytes, CXL_PARTMODE_RAM);
> + add_part(info, mds->active_volatile_bytes, mds->active_persistent_bytes,
> + CXL_PARTMODE_PMEM);
> +
> + return 0;
> +}
> +EXPORT_SYMBOL_NS_GPL(cxl_mem_dpa_fetch, "CXL");
> +
> +/**
> + * cxl_set_capacity: initialize dpa by a driver without a mailbox.
> + *
> + * @cxlds: pointer to cxl_dev_state
> + * @capacity: device volatile memory size
> + */
> +int cxl_set_capacity(struct cxl_dev_state *cxlds, u64 capacity)
> +{
> + struct cxl_dpa_info range_info = {
> + .size = capacity,
> + };
> +
> + add_part(&range_info, 0, capacity, CXL_PARTMODE_RAM);
> + return cxl_dpa_setup(cxlds, &range_info);
> +}
> +EXPORT_SYMBOL_NS_GPL(cxl_set_capacity, "CXL");
> +
> /**
> * set_exclusive_cxl_commands() - atomically disable user cxl commands
> * @mds: The device state to operate on
> diff --git a/drivers/net/ethernet/sfc/efx_cxl.c b/drivers/net/ethernet/sfc/efx_cxl.c
> index cdfbe546d8d8..651d26aa68dc 100644
> --- a/drivers/net/ethernet/sfc/efx_cxl.c
> +++ b/drivers/net/ethernet/sfc/efx_cxl.c
> @@ -78,6 +78,10 @@ int efx_cxl_init(struct efx_probe_data *probe_data)
> */
> cxl->cxlds.media_ready = true;
>
> + if (cxl_set_capacity(&cxl->cxlds, EFX_CTPIO_BUFFER_SIZE))
> + return dev_err_probe(&pci_dev->dev, -ENODEV,
> + "dpa capacity setup failed\n");
> +
> probe_data->cxl = cxl;
>
> return 0;
> diff --git a/include/cxl/cxl.h b/include/cxl/cxl.h
> index 3b9c8cb187a3..88dea6ac3769 100644
> --- a/include/cxl/cxl.h
> +++ b/include/cxl/cxl.h
> @@ -243,4 +243,5 @@ struct cxl_dev_state *_devm_cxl_dev_state_create(struct device *dev,
> int cxl_map_component_regs(const struct cxl_register_map *map,
> struct cxl_component_regs *regs,
> unsigned long map_mask);
> +int cxl_set_capacity(struct cxl_dev_state *cxlds, u64 capacity);
> #endif /* __CXL_CXL_H__ */
next prev parent reply other threads:[~2025-09-18 23:38 UTC|newest]
Thread overview: 88+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-18 9:17 [PATCH v18 00/20] Type2 device basic support alejandro.lucero-palau
2025-09-18 9:17 ` [PATCH v18 01/20] cxl: Add type2 " alejandro.lucero-palau
2025-09-18 10:55 ` Jonathan Cameron
2025-09-23 11:21 ` Alejandro Lucero Palau
2025-09-29 10:21 ` Alejandro Lucero Palau
2025-09-30 14:43 ` Jonathan Cameron
2025-09-22 21:08 ` Cheatham, Benjamin
2025-09-23 11:43 ` Alejandro Lucero Palau
2025-09-18 9:17 ` [PATCH v18 02/20] sfc: add cxl support alejandro.lucero-palau
2025-09-18 23:25 ` Dave Jiang
2025-09-18 9:17 ` [PATCH v18 03/20] cxl: Move pci generic code alejandro.lucero-palau
2025-09-22 21:10 ` Cheatham, Benjamin
2025-09-25 9:27 ` Alejandro Lucero Palau
2025-09-18 9:17 ` [PATCH v18 04/20] cxl: allow Type2 drivers to map cxl component regs alejandro.lucero-palau
2025-09-18 11:03 ` Jonathan Cameron
2025-09-24 8:25 ` Alejandro Lucero Palau
2025-09-25 8:53 ` Alejandro Lucero Palau
2025-09-18 23:30 ` Dave Jiang
2025-09-22 21:08 ` Cheatham, Benjamin
2025-09-24 8:36 ` Alejandro Lucero Palau
2025-10-01 23:20 ` PJ Waskiewicz
2025-10-02 9:36 ` Alejandro Lucero Palau
2025-10-07 21:23 ` PJ Waskiewicz
2025-09-18 9:17 ` [PATCH v18 05/20] cxl: Support dpa initialization without a mailbox alejandro.lucero-palau
2025-09-18 23:38 ` Dave Jiang [this message]
2025-09-22 21:09 ` Cheatham, Benjamin
2025-09-18 9:17 ` [PATCH v18 06/20] cxl: Prepare memdev creation for type2 alejandro.lucero-palau
2025-09-22 21:10 ` Cheatham, Benjamin
2025-09-24 8:44 ` Alejandro Lucero Palau
2025-09-18 9:17 ` [PATCH v18 07/20] sfc: create type2 cxl memdev alejandro.lucero-palau
2025-09-18 11:08 ` Jonathan Cameron
2025-09-19 15:59 ` Dave Jiang
2025-09-19 19:58 ` Dave Jiang
2025-09-24 8:56 ` Alejandro Lucero Palau
2025-09-18 9:17 ` [PATCH v18 08/20] cx/memdev: Indicate probe deferral alejandro.lucero-palau
2025-09-18 11:19 ` Jonathan Cameron
2025-09-19 17:53 ` Dave Jiang
2025-09-24 16:11 ` Alejandro Lucero Palau
2025-09-18 9:17 ` [PATCH v18 09/20] cxl: Define a driver interface for HPA free space enumeration alejandro.lucero-palau
2025-09-18 14:35 ` Jonathan Cameron
2025-09-24 16:16 ` Alejandro Lucero Palau
2025-09-30 14:47 ` Jonathan Cameron
2025-09-22 21:09 ` Cheatham, Benjamin
2025-09-24 16:53 ` Alejandro Lucero Palau
2025-09-18 9:17 ` [PATCH v18 10/20] sfc: get root decoder alejandro.lucero-palau
2025-09-19 18:20 ` Dave Jiang
2025-09-22 21:09 ` Cheatham, Benjamin
2025-09-18 9:17 ` [PATCH v18 11/20] cxl: Define a driver interface for DPA allocation alejandro.lucero-palau
2025-09-18 14:52 ` Jonathan Cameron
2025-09-25 9:18 ` Alejandro Lucero Palau
2025-09-19 19:46 ` Dave Jiang
2025-09-25 9:21 ` Alejandro Lucero Palau
2025-09-22 21:09 ` Cheatham, Benjamin
2025-09-25 9:25 ` Alejandro Lucero Palau
2025-09-18 9:17 ` [PATCH v18 12/20] sfc: get endpoint decoder alejandro.lucero-palau
2025-09-18 14:53 ` Jonathan Cameron
2025-09-25 9:45 ` Alejandro Lucero Palau
2025-09-22 21:09 ` Cheatham, Benjamin
2025-09-25 9:48 ` Alejandro Lucero Palau
2025-09-18 9:17 ` [PATCH v18 13/20] cxl: Make region type based on endpoint type alejandro.lucero-palau
2025-09-18 9:17 ` [PATCH v18 14/20] cxl/region: Factor out interleave ways setup alejandro.lucero-palau
2025-09-18 9:17 ` [PATCH v18 15/20] cxl/region: Factor out interleave granularity setup alejandro.lucero-palau
2025-09-18 9:17 ` [PATCH v18 16/20] cxl: Allow region creation by type2 drivers alejandro.lucero-palau
2025-09-18 14:58 ` Jonathan Cameron
2025-09-19 20:59 ` Dave Jiang
2025-09-26 8:59 ` Alejandro Lucero Palau
2025-09-30 0:52 ` Dave Jiang
2025-10-06 7:12 ` Alejandro Lucero Palau
2025-09-22 21:09 ` Cheatham, Benjamin
2025-09-26 9:01 ` Alejandro Lucero Palau
2025-09-18 9:17 ` [PATCH v18 17/20] cxl: Avoid dax creation for accelerators alejandro.lucero-palau
2025-09-19 21:16 ` Dave Jiang
2025-09-22 21:09 ` Cheatham, Benjamin
2025-09-18 9:17 ` [PATCH v18 18/20] sfc: create cxl region alejandro.lucero-palau
2025-09-18 15:03 ` Jonathan Cameron
2025-09-26 9:27 ` Alejandro Lucero Palau
2025-09-18 9:17 ` [PATCH v18 19/20] cxl: Add function for obtaining region range alejandro.lucero-palau
2025-09-18 9:17 ` [PATCH v18 20/20] sfc: support pio mapping based on cxl alejandro.lucero-palau
2025-09-18 15:08 ` Jonathan Cameron
2025-09-26 9:47 ` Alejandro Lucero Palau
2025-09-30 14:51 ` Jonathan Cameron
2025-09-19 12:51 ` [PATCH v18 00/20] Type2 device basic support Alejandro Lucero Palau
2025-09-19 16:26 ` Dave Jiang
2025-09-19 16:55 ` Alejandro Lucero Palau
2025-09-19 21:42 ` Dave Jiang
2025-09-23 10:35 ` Alejandro Lucero Palau
2025-09-23 18:28 ` Dave Jiang
2025-09-22 21:10 ` Cheatham, Benjamin
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