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From: Dave Jiang <dave.jiang@intel.com>
To: Neeraj Kumar <s.neeraj@samsung.com>,
	linux-cxl@vger.kernel.org, nvdimm@lists.linux.dev,
	linux-kernel@vger.kernel.org, gost.dev@samsung.com
Cc: a.manzanares@samsung.com, vishak.g@samsung.com,
	neeraj.kernel@gmail.com, cpgs@samsung.com
Subject: Re: [PATCH V3 20/20] cxl/pmem: Add CXL LSA 2.1 support in cxl pmem
Date: Wed, 24 Sep 2025 13:47:21 -0700	[thread overview]
Message-ID: <28d78d2b-c17d-4910-9f28-67af1fbb10ee@intel.com> (raw)
In-Reply-To: <20250917134116.1623730-21-s.neeraj@samsung.com>



On 9/17/25 6:41 AM, Neeraj Kumar wrote:
> Add support of CXL LSA 2.1 using NDD_REGION_LABELING flag. It creates
> cxl region based on region information parsed from LSA.
> 
> Signed-off-by: Neeraj Kumar <s.neeraj@samsung.com>
> ---
>  drivers/cxl/core/pmem_region.c | 53 ++++++++++++++++++++++++++++++++++
>  drivers/cxl/cxl.h              |  4 +++
>  drivers/cxl/pmem.c             |  2 ++
>  3 files changed, 59 insertions(+)
> 
> diff --git a/drivers/cxl/core/pmem_region.c b/drivers/cxl/core/pmem_region.c
> index 665b603c907b..3ef9c7d15041 100644
> --- a/drivers/cxl/core/pmem_region.c
> +++ b/drivers/cxl/core/pmem_region.c
> @@ -290,3 +290,56 @@ int devm_cxl_add_pmem_region(struct cxl_region *cxlr)
>  	return rc;
>  }
>  EXPORT_SYMBOL_NS_GPL(devm_cxl_add_pmem_region, "CXL");
> +
> +static int match_free_ep_decoder(struct device *dev, const void *data)
> +{
> +	struct cxl_decoder *cxld = to_cxl_decoder(dev);

I think this is needed if the function is match_free_ep_decoder().

if (!is_endpoint_decoder(dev))
	return 0;

> +
> +	return !cxld->region;
> +}

May want to borrow some code from match_free_decoder() in core/region.c. I think the decoder commit order matters?

> +
> +static struct cxl_decoder *cxl_find_free_ep_decoder(struct cxl_port *port)
> +{
> +	struct device *dev;
> +
> +	dev = device_find_child(&port->dev, NULL, match_free_ep_decoder);
> +	if (!dev)
> +		return NULL;
> +
> +	/* Release device ref taken via device_find_child() */
> +	put_device(dev);

Should have the caller put the device.

> +	return to_cxl_decoder(dev);
> +}
> +
> +void create_pmem_region(struct nvdimm *nvdimm)
> +{
> +	struct cxl_nvdimm *cxl_nvd;
> +	struct cxl_memdev *cxlmd;
> +	struct cxl_pmem_region_params *params;
> +	struct cxl_root_decoder *cxlrd;
> +	struct cxl_decoder *cxld;
> +	struct cxl_region *cxlr;
> +
> +	if (!nvdimm_has_cxl_region(nvdimm))
> +		return;
> +
> +	lockdep_assert_held(&cxl_rwsem.region);
> +	cxl_nvd = nvdimm_provider_data(nvdimm);
> +	params = nvdimm_get_cxl_region_param(nvdimm);
> +	cxlmd = cxl_nvd->cxlmd;
> +	cxlrd = cxlmd->cxlrd;
> +
> +	 /* TODO: Region creation support only for interleave way == 1 */
> +	if (!(params->nlabel == 1))
> +		dev_info(&cxlmd->dev,
> +			 "Region Creation is not supported with iw > 1\n");

Why not just exit here. Then the else is not necessary.

Also maybe deb_dbg().

> +	else {
> +		cxld = cxl_find_free_ep_decoder(cxlmd->endpoint);
> +		cxlr = cxl_create_region(cxlrd, CXL_PARTMODE_PMEM,
> +					 atomic_read(&cxlrd->region_id),
> +					 params, cxld);
> +		if (IS_ERR(cxlr))
> +			dev_info(&cxlmd->dev, "Region Creation failed\n");

dev_warn()

> +	}
> +}
> +EXPORT_SYMBOL_NS_GPL(create_pmem_region, "CXL");
> diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
> index f01f8c942fdf..0a87ea79742a 100644
> --- a/drivers/cxl/cxl.h
> +++ b/drivers/cxl/cxl.h
> @@ -910,6 +910,7 @@ cxl_create_region(struct cxl_root_decoder *cxlrd,
>  bool is_cxl_pmem_region(struct device *dev);
>  struct cxl_pmem_region *to_cxl_pmem_region(struct device *dev);
>  int devm_cxl_add_pmem_region(struct cxl_region *cxlr);
> +void create_pmem_region(struct nvdimm *nvdimm);
>  #else
>  static inline bool is_cxl_pmem_region(struct device *dev)
>  {
> @@ -923,6 +924,9 @@ static inline int devm_cxl_add_pmem_region(struct cxl_region *cxlr)
>  {
>  	return 0;
>  }
> +static inline void create_pmem_region(struct nvdimm *nvdimm)
> +{
> +}
>  #endif
>  
>  void cxl_endpoint_parse_cdat(struct cxl_port *port);
> diff --git a/drivers/cxl/pmem.c b/drivers/cxl/pmem.c
> index 38a5bcdc68ce..0cdef01dbc68 100644
> --- a/drivers/cxl/pmem.c
> +++ b/drivers/cxl/pmem.c
> @@ -135,6 +135,7 @@ static int cxl_nvdimm_probe(struct device *dev)
>  		return rc;
>  
>  	set_bit(NDD_LABELING, &flags);
> +	set_bit(NDD_REGION_LABELING, &flags);
>  	set_bit(NDD_REGISTER_SYNC, &flags);
>  	set_bit(ND_CMD_GET_CONFIG_SIZE, &cmd_mask);
>  	set_bit(ND_CMD_GET_CONFIG_DATA, &cmd_mask);
> @@ -155,6 +156,7 @@ static int cxl_nvdimm_probe(struct device *dev)
>  		return -ENOMEM;
>  
>  	dev_set_drvdata(dev, nvdimm);
> +	create_pmem_region(nvdimm);
>  	return devm_add_action_or_reset(dev, unregister_nvdimm, nvdimm);
>  }
>  


  reply	other threads:[~2025-09-24 20:47 UTC|newest]

Thread overview: 89+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <CGME20250917134126epcas5p3e20c773759b91f70a1caa32b9f6f27ff@epcas5p3.samsung.com>
2025-09-17 13:40 ` [PATCH V3 00/20] Add CXL LSA 2.1 format support in nvdimm and cxl pmem Neeraj Kumar
2025-09-17 13:40   ` [PATCH V3 01/20] nvdimm/label: Introduce NDD_REGION_LABELING flag to set region label Neeraj Kumar
2025-09-19 23:10     ` Dave Jiang
2025-09-22 12:41       ` Neeraj Kumar
2025-09-17 13:40   ` [PATCH V3 02/20] nvdimm/label: CXL labels skip the need for 'interleave-set cookie' Neeraj Kumar
2025-09-19 23:31     ` Dave Jiang
2025-09-17 13:40   ` [PATCH V3 03/20] nvdimm/label: Modify nd_label_base() signature Neeraj Kumar
2025-09-19 21:42     ` Ira Weiny
2025-09-19 23:34     ` Dave Jiang
2025-09-22 12:44       ` Neeraj Kumar
2025-09-24 21:02         ` Alison Schofield
2025-09-29 14:07           ` Neeraj Kumar
2025-09-17 13:41   ` [PATCH V3 04/20] nvdimm/label: Update mutex_lock() with guard(mutex)() Neeraj Kumar
2025-09-19 21:55     ` Ira Weiny
2025-09-22 12:56       ` Neeraj Kumar
2025-09-19 23:50     ` Dave Jiang
2025-09-20 17:44       ` Ira Weiny
2025-09-22 13:01         ` Neeraj Kumar
2025-09-24 21:42     ` Alison Schofield
2025-09-29 14:19       ` Neeraj Kumar
2025-09-17 13:41   ` [PATCH V3 05/20] nvdimm/namespace_label: Add namespace label changes as per CXL LSA v2.1 Neeraj Kumar
2025-09-17 14:54     ` Jonathan Cameron
2025-09-19 22:00     ` Ira Weiny
2025-09-22 13:05       ` Neeraj Kumar
2025-09-19 23:59     ` Dave Jiang
2025-09-22 13:03       ` Neeraj Kumar
2025-09-23 21:48     ` Dave Jiang
2025-09-29 13:28       ` Neeraj Kumar
2025-09-17 13:41   ` [PATCH V3 06/20] nvdimm/region_label: Add region label update support Neeraj Kumar
2025-09-17 15:36     ` Jonathan Cameron
2025-09-22 13:12       ` Neeraj Kumar
2025-10-06 16:56       ` Dave Jiang
2025-09-22 23:11     ` Dave Jiang
2025-09-29 13:24       ` Neeraj Kumar
2025-09-17 13:41   ` [PATCH V3 07/20] nvdimm/region_label: Add region label delete support Neeraj Kumar
2025-09-22 21:37     ` Dave Jiang
2025-09-29 13:13       ` Neeraj Kumar
2025-09-17 13:41   ` [PATCH V3 08/20] nvdimm/label: Include region label in slot validation Neeraj Kumar
2025-09-22 22:17     ` Dave Jiang
2025-09-29 13:17       ` Neeraj Kumar
2025-09-24 21:30     ` Alison Schofield
2025-09-29 14:10       ` Neeraj Kumar
2025-09-17 13:41   ` [PATCH V3 09/20] nvdimm/namespace_label: Skip region label during ns label DPA reservation Neeraj Kumar
2025-09-17 13:41   ` [PATCH V3 10/20] nvdimm/namespace_label: Skip region label during namespace creation Neeraj Kumar
2025-09-17 13:41   ` [PATCH V3 11/20] nvdimm/region_label: Preserve cxl region information from region label Neeraj Kumar
2025-09-17 13:41   ` [PATCH V3 12/20] nvdimm/region_label: Export routine to fetch region information Neeraj Kumar
2025-09-23 20:23     ` Dave Jiang
2025-09-29 13:26       ` Neeraj Kumar
2025-09-17 13:41   ` [PATCH V3 13/20] cxl/mem: Refactor cxl pmem region auto-assembling Neeraj Kumar
2025-09-23 22:37     ` Dave Jiang
2025-09-29 13:30       ` Neeraj Kumar
2025-10-06 15:55         ` Dave Jiang
2025-11-07 12:39           ` Neeraj Kumar
2025-11-12 15:55             ` Dave Jiang
2025-11-13  7:27               ` Neeraj Kumar
2025-09-17 13:41   ` [PATCH V3 14/20] cxl/region: Add devm_cxl_pmem_add_region() for pmem region creation Neeraj Kumar
2025-09-23 23:50     ` Dave Jiang
2025-09-29 13:37       ` Neeraj Kumar
2025-09-17 13:41   ` [PATCH V3 15/20] cxl: Add a routine to find cxl root decoder on cxl bus using cxl port Neeraj Kumar
2025-09-24 18:11     ` Dave Jiang
2025-09-29 13:40       ` Neeraj Kumar
2025-10-06 16:02         ` Dave Jiang
2025-09-17 13:41   ` [PATCH V3 16/20] cxl/mem: Preserve cxl root decoder during mem probe Neeraj Kumar
2025-09-24 18:23     ` Dave Jiang
2025-09-29 13:52       ` Neeraj Kumar
2025-09-24 21:38     ` Alison Schofield
2025-09-29 14:13       ` Neeraj Kumar
2025-09-17 13:41   ` [PATCH V3 17/20] cxl/pmem: Preserve region information into nd_set Neeraj Kumar
2025-09-17 13:41   ` [PATCH V3 18/20] cxl/pmem_region: Prep patch to accommodate pmem_region attributes Neeraj Kumar
2025-09-24 18:53     ` Dave Jiang
2025-09-29 13:57       ` Neeraj Kumar
2025-10-06 16:06         ` Dave Jiang
2025-11-07 12:49           ` Neeraj Kumar
2025-11-12 15:40             ` Dave Jiang
2025-11-13  7:29               ` Neeraj Kumar
2025-10-06 16:09         ` Dave Jiang
2025-09-17 13:41   ` [PATCH V3 19/20] cxl/pmem_region: Add sysfs attribute cxl region label updation/deletion Neeraj Kumar
2025-09-24 20:25     ` Dave Jiang
2025-09-29 14:00       ` Neeraj Kumar
2025-09-17 13:41   ` [PATCH V3 20/20] cxl/pmem: Add CXL LSA 2.1 support in cxl pmem Neeraj Kumar
2025-09-24 20:47     ` Dave Jiang [this message]
2025-09-29 14:02       ` Neeraj Kumar
2025-10-06 16:13         ` Dave Jiang
2025-09-17 14:50   ` [PATCH V3 00/20] Add CXL LSA 2.1 format support in nvdimm and " Jonathan Cameron
2025-09-17 15:38     ` Dave Jiang
2025-09-22 12:36     ` Neeraj Kumar
2025-09-23 23:04   ` Alison Schofield
2025-09-29 13:33     ` Neeraj Kumar
     [not found] <CGME20250917133058epcas5p33af456c574a095b53001521358bae67a@epcas5p3.samsung.com>
2025-09-17 13:29 ` Neeraj Kumar
2025-09-17 13:29   ` [PATCH V3 20/20] cxl/pmem: Add CXL LSA 2.1 support in " Neeraj Kumar

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