From: Alejandro Lucero Palau <alucerop@amd.com>
To: Ben Cheatham <benjamin.cheatham@amd.com>, alejandro.lucero-palau@amd.com
Cc: linux-cxl@vger.kernel.org, netdev@vger.kernel.org,
dan.j.williams@intel.com, edward.cree@amd.com,
davem@davemloft.net, kuba@kernel.org, pabeni@redhat.com,
edumazet@google.com, dave.jiang@intel.com
Subject: Re: [PATCH v11 18/23] cxl: allow region creation by type2 drivers
Date: Wed, 12 Mar 2025 08:28:53 +0000 [thread overview]
Message-ID: <311bcb0d-0ba2-46d0-acc3-87c119cd9e54@amd.com> (raw)
In-Reply-To: <c5067d20-1804-4c14-b0cc-3e27b119f67a@amd.com>
On 3/11/25 20:06, Ben Cheatham wrote:
> On 3/10/25 4:03 PM, alejandro.lucero-palau@amd.com wrote:
>> From: Alejandro Lucero <alucerop@amd.com>
>>
>> Creating a CXL region requires userspace intervention through the cxl
>> sysfs files. Type2 support should allow accelerator drivers to create
>> such cxl region from kernel code.
>>
>> Adding that functionality and integrating it with current support for
>> memory expanders.
>>
>> Based on https://lore.kernel.org/linux-cxl/168592159835.1948938.1647215579839222774.stgit@dwillia2-xfh.jf.intel.com/
>>
>> Signed-off-by: Alejandro Lucero <alucerop@amd.com>
>> ---
>> drivers/cxl/core/region.c | 133 +++++++++++++++++++++++++++++++++++---
>> drivers/cxl/port.c | 5 +-
>> include/cxl/cxl.h | 4 ++
>> 3 files changed, 133 insertions(+), 9 deletions(-)
>>
>> diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c
>> index e24666a419cd..e6fbe00d0623 100644
>> --- a/drivers/cxl/core/region.c
>> +++ b/drivers/cxl/core/region.c
>> @@ -2310,6 +2310,17 @@ static int cxl_region_detach(struct cxl_endpoint_decoder *cxled)
>> return rc;
>> }
>>
>> +int cxl_accel_region_detach(struct cxl_endpoint_decoder *cxled)
>> +{
>> + int rc;
>> +
>> + guard(rwsem_write)(&cxl_region_rwsem);
>> + cxled->part = -1;
>> + rc = cxl_region_detach(cxled);
>> + return rc;
>> +}
>> +EXPORT_SYMBOL_NS_GPL(cxl_accel_region_detach, "CXL");
>> +
>> void cxl_decoder_kill_region(struct cxl_endpoint_decoder *cxled)
>> {
>> down_write(&cxl_region_rwsem);
>> @@ -2816,6 +2827,14 @@ cxl_find_region_by_name(struct cxl_root_decoder *cxlrd, const char *name)
>> return to_cxl_region(region_dev);
>> }
>>
>> +static void drop_region(struct cxl_region *cxlr)
>> +{
>> + struct cxl_root_decoder *cxlrd = to_cxl_root_decoder(cxlr->dev.parent);
>> + struct cxl_port *port = cxlrd_to_port(cxlrd);
>> +
>> + devm_release_action(port->uport_dev, unregister_region, cxlr);
>> +}
>> +
> Nit: There are a couple of spots in this file that call the above devm_release_action,
> I think it would be good to replace those with a call to this function. You
> could also get rid of drop_region() and use devm_release_action() instead.
I'll take a look.
>> static ssize_t delete_region_store(struct device *dev,
>> struct device_attribute *attr,
>> const char *buf, size_t len)
> [snip]
>
>> +/**
>> + * cxl_create_region - Establish a region given an endpoint decoder
>> + * @cxlrd: root decoder to allocate HPA
>> + * @cxled: endpoint decoder with reserved DPA capacity
>> + *
>> + * Returns a fully formed region in the commit state and attached to the
>> + * cxl_region driver.
>> + */
>> +struct cxl_region *cxl_create_region(struct cxl_root_decoder *cxlrd,
>> + struct cxl_endpoint_decoder *cxled, int ways)
> Sorry if I'm behind the times, but is it no longer a requirement for accelerator drivers
> to have interleaving disabled (i.e. interleave_ways = 1)?
It is unlikely but there is no restriction by the specs and Dan
suggested supporting this situation was not complicated, so better to do
it from the start.
next prev parent reply other threads:[~2025-03-12 8:29 UTC|newest]
Thread overview: 55+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-10 21:03 [PATCH v11 00/23] add type2 device basic support alejandro.lucero-palau
2025-03-10 21:03 ` [PATCH v11 01/23] cxl: " alejandro.lucero-palau
2025-03-11 20:05 ` Ben Cheatham
2025-03-12 8:20 ` Alejandro Lucero Palau
2025-03-12 20:00 ` Alison Schofield
2025-03-17 7:56 ` Alejandro Lucero Palau
2025-03-10 21:03 ` [PATCH v11 02/23] sfc: add cxl support alejandro.lucero-palau
2025-03-10 21:03 ` [PATCH v11 03/23] cxl: move pci generic code alejandro.lucero-palau
2025-03-11 20:05 ` Ben Cheatham
2025-03-12 8:26 ` Alejandro Lucero Palau
2025-03-10 21:03 ` [PATCH v11 04/23] cxl: move register/capability check to driver alejandro.lucero-palau
2025-03-11 20:05 ` Ben Cheatham
2025-03-25 14:21 ` Alejandro Lucero Palau
2025-03-10 21:03 ` [PATCH v11 05/23] cxl: add function for type2 cxl regs setup alejandro.lucero-palau
2025-03-11 20:05 ` Ben Cheatham
2025-03-10 21:03 ` [PATCH v11 06/23] sfc: make regs setup with checking and set media ready alejandro.lucero-palau
2025-03-10 21:03 ` [PATCH v11 07/23] cxl: support dpa initialization without a mailbox alejandro.lucero-palau
2025-03-11 20:05 ` Ben Cheatham
2025-03-10 21:03 ` [PATCH v11 08/23] sfc: initialize dpa alejandro.lucero-palau
2025-03-10 21:03 ` [PATCH v11 09/23] cxl: prepare memdev creation for type2 alejandro.lucero-palau
2025-03-11 20:05 ` Ben Cheatham
2025-03-10 21:03 ` [PATCH v11 10/23] sfc: create type2 cxl memdev alejandro.lucero-palau
2025-03-10 21:03 ` [PATCH v11 11/23] cxl: define a driver interface for HPA free space enumeration alejandro.lucero-palau
2025-03-11 20:06 ` Ben Cheatham
2025-03-25 15:07 ` Alejandro Lucero Palau
2025-03-25 15:46 ` Ben Cheatham
2025-03-10 21:03 ` [PATCH v11 12/23] fc: obtain root decoder with enough HPA free space alejandro.lucero-palau
2025-03-10 21:03 ` [PATCH v11 13/23] cxl: define a driver interface for DPA allocation alejandro.lucero-palau
2025-03-11 19:12 ` kernel test robot
2025-03-11 20:06 ` Ben Cheatham
2025-03-11 20:17 ` kernel test robot
2025-03-20 16:18 ` Simon Horman
2025-03-24 16:16 ` Alejandro Lucero Palau
2025-03-25 15:23 ` Simon Horman
2025-03-10 21:03 ` [PATCH v11 14/23] sfc: get endpoint decoder alejandro.lucero-palau
2025-03-10 21:03 ` [PATCH v11 15/23] cxl: make region type based on endpoint type alejandro.lucero-palau
2025-03-11 20:06 ` Ben Cheatham
2025-03-10 21:03 ` [PATCH v11 16/23] cxl/region: factor out interleave ways setup alejandro.lucero-palau
2025-03-11 20:06 ` Ben Cheatham
2025-03-10 21:03 ` [PATCH v11 17/23] cxl/region: factor out interleave granularity setup alejandro.lucero-palau
2025-03-11 20:06 ` Ben Cheatham
2025-03-10 21:03 ` [PATCH v11 18/23] cxl: allow region creation by type2 drivers alejandro.lucero-palau
2025-03-11 20:06 ` Ben Cheatham
2025-03-12 8:28 ` Alejandro Lucero Palau [this message]
2025-03-20 16:21 ` Simon Horman
2025-03-10 21:03 ` [PATCH v11 19/23] cxl: add region flag for precluding a device memory to be used for dax alejandro.lucero-palau
2025-03-11 20:06 ` Ben Cheatham
2025-03-10 21:03 ` [PATCH v11 20/23] sfc: create cxl region alejandro.lucero-palau
2025-03-10 21:03 ` [PATCH v11 21/23] cxl: add function for obtaining region range alejandro.lucero-palau
2025-03-11 20:06 ` Ben Cheatham
2025-03-10 21:03 ` [PATCH v11 22/23] sfc: update MCDI protocol headers alejandro.lucero-palau
2025-03-10 21:03 ` [PATCH v11 23/23] sfc: support pio mapping based on cxl alejandro.lucero-palau
2025-03-12 6:42 ` kernel test robot
2025-03-12 17:57 ` [PATCH v11 00/23] add type2 device basic support Alison Schofield
2025-03-17 7:55 ` Alejandro Lucero Palau
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