From: Ben Cheatham <benjamin.cheatham@amd.com>
To: Alejandro Lucero Palau <alucerop@amd.com>,
<alejandro.lucero-palau@amd.com>
Cc: Jonathan Cameron <Jonathan.Cameron@huawei.com>,
<linux-cxl@vger.kernel.org>, <netdev@vger.kernel.org>,
<dan.j.williams@intel.com>, <edward.cree@amd.com>,
<davem@davemloft.net>, <kuba@kernel.org>, <pabeni@redhat.com>,
<edumazet@google.com>, <dave.jiang@intel.com>
Subject: Re: [PATCH v11 11/23] cxl: define a driver interface for HPA free space enumeration
Date: Tue, 25 Mar 2025 10:46:05 -0500 [thread overview]
Message-ID: <ab4f2017-9e40-4923-8f6e-6514a511dd4c@amd.com> (raw)
In-Reply-To: <72025133-8d0e-4ae8-af7a-410c1aaced06@amd.com>
>>> +
>>> + for (int i = 0; i < ctx->interleave_ways; i++)
>>> + for (int j = 0; j < ctx->interleave_ways; j++)
>>> + if (ctx->host_bridges[i] == cxlsd->target[j]->dport_dev) {
>>> + found++;
>>> + break;
>>> + }
>> I think kernel coding style requires braces on the above for statements, but I may be wrong here.
>
>
> I can not see a specific reference to this case. But, do you mean both for clauses requiring it or just the second one?
>
I think it should be:
for (int i = 0; i < ctx->interleave_ways; i++) {
for (int j = 0 ; j < ctx->interleave_ways; j++) {
...
}
}
But it's a style nit, if whoever is taking the patch doesn't care then I don't really either.
>
[snip]
>>> +
>>> +/**
>>> + * cxl_get_hpa_freespace - find a root decoder with free capacity per constraints
>>> + * @cxlmd: the CXL memory device with an endpoint that is mapped by the returned
>>> + * decoder
>>> + * @interleave_ways: number of entries in @host_bridges
>>> + * @flags: CXL_DECODER_F flags for selecting RAM vs PMEM, and HDM-H vs HDM-D[B]
>> Looking below, the HDM-H vs HDM-D[B] flag is called CXL_DECODER_F_TYPE2, so I think
>> it would be good to reference that either here or in include/cxl/cxl.h.
>
>
> Well, it is not that but I agree the description requires an update like;
>
>
> "flags for selecting RAM vs PMEM, and Type2 device."
>
>
> I think because the patch does not define the HDM-* as it is not needed yet, it should not be there.
>
Sounds good to me.
Thanks,
Ben
next prev parent reply other threads:[~2025-03-25 15:46 UTC|newest]
Thread overview: 55+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-10 21:03 [PATCH v11 00/23] add type2 device basic support alejandro.lucero-palau
2025-03-10 21:03 ` [PATCH v11 01/23] cxl: " alejandro.lucero-palau
2025-03-11 20:05 ` Ben Cheatham
2025-03-12 8:20 ` Alejandro Lucero Palau
2025-03-12 20:00 ` Alison Schofield
2025-03-17 7:56 ` Alejandro Lucero Palau
2025-03-10 21:03 ` [PATCH v11 02/23] sfc: add cxl support alejandro.lucero-palau
2025-03-10 21:03 ` [PATCH v11 03/23] cxl: move pci generic code alejandro.lucero-palau
2025-03-11 20:05 ` Ben Cheatham
2025-03-12 8:26 ` Alejandro Lucero Palau
2025-03-10 21:03 ` [PATCH v11 04/23] cxl: move register/capability check to driver alejandro.lucero-palau
2025-03-11 20:05 ` Ben Cheatham
2025-03-25 14:21 ` Alejandro Lucero Palau
2025-03-10 21:03 ` [PATCH v11 05/23] cxl: add function for type2 cxl regs setup alejandro.lucero-palau
2025-03-11 20:05 ` Ben Cheatham
2025-03-10 21:03 ` [PATCH v11 06/23] sfc: make regs setup with checking and set media ready alejandro.lucero-palau
2025-03-10 21:03 ` [PATCH v11 07/23] cxl: support dpa initialization without a mailbox alejandro.lucero-palau
2025-03-11 20:05 ` Ben Cheatham
2025-03-10 21:03 ` [PATCH v11 08/23] sfc: initialize dpa alejandro.lucero-palau
2025-03-10 21:03 ` [PATCH v11 09/23] cxl: prepare memdev creation for type2 alejandro.lucero-palau
2025-03-11 20:05 ` Ben Cheatham
2025-03-10 21:03 ` [PATCH v11 10/23] sfc: create type2 cxl memdev alejandro.lucero-palau
2025-03-10 21:03 ` [PATCH v11 11/23] cxl: define a driver interface for HPA free space enumeration alejandro.lucero-palau
2025-03-11 20:06 ` Ben Cheatham
2025-03-25 15:07 ` Alejandro Lucero Palau
2025-03-25 15:46 ` Ben Cheatham [this message]
2025-03-10 21:03 ` [PATCH v11 12/23] fc: obtain root decoder with enough HPA free space alejandro.lucero-palau
2025-03-10 21:03 ` [PATCH v11 13/23] cxl: define a driver interface for DPA allocation alejandro.lucero-palau
2025-03-11 19:12 ` kernel test robot
2025-03-11 20:06 ` Ben Cheatham
2025-03-11 20:17 ` kernel test robot
2025-03-20 16:18 ` Simon Horman
2025-03-24 16:16 ` Alejandro Lucero Palau
2025-03-25 15:23 ` Simon Horman
2025-03-10 21:03 ` [PATCH v11 14/23] sfc: get endpoint decoder alejandro.lucero-palau
2025-03-10 21:03 ` [PATCH v11 15/23] cxl: make region type based on endpoint type alejandro.lucero-palau
2025-03-11 20:06 ` Ben Cheatham
2025-03-10 21:03 ` [PATCH v11 16/23] cxl/region: factor out interleave ways setup alejandro.lucero-palau
2025-03-11 20:06 ` Ben Cheatham
2025-03-10 21:03 ` [PATCH v11 17/23] cxl/region: factor out interleave granularity setup alejandro.lucero-palau
2025-03-11 20:06 ` Ben Cheatham
2025-03-10 21:03 ` [PATCH v11 18/23] cxl: allow region creation by type2 drivers alejandro.lucero-palau
2025-03-11 20:06 ` Ben Cheatham
2025-03-12 8:28 ` Alejandro Lucero Palau
2025-03-20 16:21 ` Simon Horman
2025-03-10 21:03 ` [PATCH v11 19/23] cxl: add region flag for precluding a device memory to be used for dax alejandro.lucero-palau
2025-03-11 20:06 ` Ben Cheatham
2025-03-10 21:03 ` [PATCH v11 20/23] sfc: create cxl region alejandro.lucero-palau
2025-03-10 21:03 ` [PATCH v11 21/23] cxl: add function for obtaining region range alejandro.lucero-palau
2025-03-11 20:06 ` Ben Cheatham
2025-03-10 21:03 ` [PATCH v11 22/23] sfc: update MCDI protocol headers alejandro.lucero-palau
2025-03-10 21:03 ` [PATCH v11 23/23] sfc: support pio mapping based on cxl alejandro.lucero-palau
2025-03-12 6:42 ` kernel test robot
2025-03-12 17:57 ` [PATCH v11 00/23] add type2 device basic support Alison Schofield
2025-03-17 7:55 ` Alejandro Lucero Palau
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