Re: [PATCH v14 0/2] Export cxl1.1 device link status register value to pci device sysfs.

[Dave Jiang <dave.jiang@intel.com>]

On 7/7/24 8:05 PM, Daisuke Kobayashi (Fujitsu) wrote:
> 
> Kobayashi Daisuke wrote:
>> CXL devices are extensions of PCIe. Therefore, from CXL2.0 onwards, the link
>> status can be output in the same way as traditional PCIe.
>> However, unlike devices from CXL2.0 onwards, CXL1.1 requires a different
>> method to obtain the link status from traditional PCIe.
>> This is because the link status of the CXL1.1 device is not mapped in the
>> configuration space (as per cxl3.0 specification 8.1).
>> Instead, the configuration space containing the link status is mapped to the
>> memory mapped register region (as per cxl3.0 specification 8.2, Table 8-18).
>> Therefore, the current lspci has a problem where it does not display the link
>> status of the CXL1.1 device.
>> Solve these issues with sysfs attributes to export the status registers hidden in
>> the RCRB.
>>
>> The procedure is as follows:
>> First, obtain the RCRB address within the cxl driver, then access the
>> configuration space. Next, output the link status information from the
>> configuration space to sysfs. Ultimately, the expectation is that this sysfs file
>> will be consumed by PCI user tools to utilize link status information.
>>
>>
>> Changes
>> v1[1] -> v2:
>> - Modified to perform rcrb access within the CXL driver.
>> - Added new attributes to the sysfs of the PCI device.
>> - Output the link status information to the sysfs of the PCI device.
>> - Retrieve information from sysfs as the source when displaying information in
>> lspci.
>>
>> v2[2] -> v3:
>> - Fix unnecessary initialization and wrong types (Bjohn).
>> - Create a helper function for getting a PCIe capability offset (Bjohn).
>> - Move platform-specific implementation to the lib directory in pciutils
>> (Martin).
>>
>> v3[3] -> v4:
>> - RCRB register values are read once and cached.
>> - Added a new attribute to the sysfs of the PCI device.
>> - Separate lspci implementation from this patch.
>>
>> v4[4] -> v5:
>> - Use macros for bitwise operations
>> - Fix RCRB access to use cxl_memdev
>>
>> v5[5] -> v6:
>> - Add and use masks for RCRB register values
>>
>> v6[6] -> v7:
>> - Fix comments on white space inline
>>
>> v7[7] -> v8:
>> - Change the cache value to offset
>> - Access memory map area in rcd_*_show() functions
>>
>> v8[8] -> v9:
>> - Map the pcie cap in for all the time the driver is bound to the device.
>> - Add mapping the pcie cap in cxl_rcd_component_reg_phys().
>>
>> v9[9] -> v10:
>> - Change a utility function for getting PCIe capability.
>> - Fix tab alignment issue, error handling, and apply suggestions from Jonathan.
>>
>> v10[10] -> v11:
>> - Add functions to have one function do only one thing.
>> - Add a size parameter to utility function arguments and consolidated them into
>> one.
>>
>> v11[11] -> v12:
>> - Fix the error handling in cxl_pci_setup_regs().
>> - Fix and clean up some details.
>>
>> v12[12] -> v13:
>> - Fix and clean up some details.
>>
>> v13[13] -> v14:
>> - Fix and clean up some details.
>>
>> [1]
>> https://lore.kernel.org/linux-cxl/20231220050738.178481-1-kobayashi.da-06
>> @fujitsu.com/
>> [2]
>> https://lore.kernel.org/linux-cxl/20240227083313.87699-1-kobayashi.da-06@
>> fujitsu.com/
>> [3]
>> https://lore.kernel.org/linux-cxl/20240312080559.14904-1-kobayashi.da-06@
>> fujitsu.com/
>> [4]
>> https://lore.kernel.org/linux-cxl/20240409073528.13214-1-kobayashi.da-06@
>> fujitsu.com/
>> [5]
>> https://lore.kernel.org/linux-cxl/20240412070715.16160-1-kobayashi.da-06@
>> fujitsu.com/
>> [6]
>> https://lore.kernel.org/linux-cxl/20240424050102.26788-1-kobayashi.da-06@
>> fujitsu.com/
>> [7]
>> https://lore.kernel.org/linux-cxl/20240510073710.98953-1-kobayashi.da-06@
>> fujitsu.com/
>> [8]
>> https://lore.kernel.org/linux-cxl/20240606074814.5633-1-kobayashi.da-06@f
>> ujitsu.com/
>> [9]
>> https://lore.kernel.org/linux-cxl/20240610082222.22772-1-kobayashi.da-06@
>> fujitsu.com/
>> [10]
>> https://lore.kernel.org/linux-cxl/20240611055254.61203-1-kobayashi.da-06@
>> fujitsu.com/
>> [11]
>> https://lore.kernel.org/linux-cxl/20240612075940.92500-1-kobayashi.da-06@
>> fujitsu.com/
>> [12]
>> https://lore.kernel.org/linux-cxl/20240614045611.58658-1-kobayashi.da-06@
>> fujitsu.com/
>> [13]
>> https://lore.kernel.org/linux-cxl/20240617043702.62028-1-kobayashi.da-06@
>> fujitsu.com/
>>
>> Kobayashi,Daisuke (2):
>>   cxl/core/regs: Add rcd_pcie_cap initialization
>>   cxl/pci: Add sysfs attribute for CXL 1.1 device link status
>>
>>  drivers/cxl/core/core.h |  6 +++
>>  drivers/cxl/core/regs.c | 61 ++++++++++++++++++++++++++++
>>  drivers/cxl/cxl.h       |  9 +++++
>>  drivers/cxl/pci.c       | 89
>> ++++++++++++++++++++++++++++++++++++++++-
>>  4 files changed, 163 insertions(+), 2 deletions(-)
>>
>> --
>> 2.44.0
> 
> Can you merge this patch into the next kernel?
> It has been reviewed and I believe it is ready to be merged.
> If it is already in process, please let me know as it is my fault for not checking thoroughly.

I'm waiting on review tags from Dan for this series. As I recall he had some previous comments. 
>