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From: Dan Williams <dan.j.williams@intel.com>
To: Dan Williams <dan.j.williams@intel.com>,
	"Kobayashi,Daisuke" <kobayashi.da-06@fujitsu.com>,
	<kobayashi.da-06@jp.fujitsu.com>, <linux-cxl@vger.kernel.org>
Cc: <y-goto@fujitsu.com>, <mj@ucw.cz>, <dan.j.williams@intel.com>,
	<jonathan.cameron@huawei.com>,
	"Kobayashi,Daisuke" <kobayashi.da-06@fujitsu.com>
Subject: Re: [PATCH v14 1/2] cxl/core/regs: Add rcd_pcie_cap initialization
Date: Tue, 9 Jul 2024 23:08:37 -0700	[thread overview]
Message-ID: <668e256583728_6de229444@dwillia2-mobl3.amr.corp.intel.com.notmuch> (raw)
In-Reply-To: <668df392f2036_102cc2949a@dwillia2-xfh.jf.intel.com.notmuch>

Dan Williams wrote:
> Kobayashi,Daisuke wrote:
> > Add rcd_pcie_cap and its initialization to cache the offset of cxl1.1 
> > device link status information. By caching it, avoid the walking 
> > memory map area to find the offset when output the register value.
> > 
> > Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> > Signed-off-by: "Kobayashi,Daisuke" <kobayashi.da-06@fujitsu.com>
> > ---
> >  drivers/cxl/core/core.h |  6 ++++
> >  drivers/cxl/core/regs.c | 61 +++++++++++++++++++++++++++++++++++++++++
> >  drivers/cxl/cxl.h       |  9 ++++++
> >  drivers/cxl/pci.c       |  8 ++++--
> >  4 files changed, 82 insertions(+), 2 deletions(-)
> > 
[..]
> > diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
> > index 2ff361e756d6..bbc55732d6c1 100644
> > --- a/drivers/cxl/pci.c
> > +++ b/drivers/cxl/pci.c
> > @@ -512,11 +512,15 @@ static int cxl_pci_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type,
> >  	 * is an RCH and try to extract the Component Registers from
> >  	 * an RCRB.
> >  	 */
> > -	if (rc && type == CXL_REGLOC_RBI_COMPONENT && is_cxl_restricted(pdev))
> > +	if (rc && type == CXL_REGLOC_RBI_COMPONENT && is_cxl_restricted(pdev)) {
> >  		rc = cxl_rcrb_get_comp_regs(pdev, map);
> > +		if (rc)
> > +			return rc;
> >  
> > -	if (rc)
> > +		cxl_dport_map_rcd_linkcap(pdev);
> 
[..]
> Ugh, I was going to say copy what cxl_mem_probe() does around locking
> endpoint_parent before attaching further ports, but that also appears to
> not handle the same race. I.e. I think cxl_mem_probe() needs a fix to do
> this as well. I will copy you on a proposed patch for that.

I attempted to add the proper locking to keep cxl_dport live, but that
runs into lockdep issues.

So I think a better fix is rework dport lifetime to stay alive until the
final put_device() of the port. In other words dport instances get added
dynamically to the cxl_port, but only get destroyed after all port
references are dropped. Then the @dport result from find_cxl_port() is
not ephemeral.

Given this is a latent bug that affects all current
cxl_{mem,pci}_find_port() users, the planned fix is to just make dport
lifetime longer, and that I will not have time to do that rework before
v6.11 merge window, then I am ok for this lnkcap code to introduce
another instance of the same bug.

So, just make cxl_rcrb_get_comp_regs() and cxl_dport_map_rcd_linkcap()
share the same port reference from one cxl_pci_find_port() call.

  reply	other threads:[~2024-07-10  6:08 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-06-18  4:29 [PATCH v14 0/2] Export cxl1.1 device link status register value to pci device sysfs Kobayashi,Daisuke
2024-06-18  4:29 ` [PATCH v14 1/2] cxl/core/regs: Add rcd_pcie_cap initialization Kobayashi,Daisuke
2024-07-10  2:36   ` Dan Williams
2024-07-10  6:08     ` Dan Williams [this message]
2024-07-10  8:10       ` Daisuke Kobayashi (Fujitsu)
2024-07-11  1:34         ` Dan Williams
2024-06-18  4:29 ` [PATCH v14 2/2] cxl/pci: Add sysfs attribute for CXL 1.1 device link status Kobayashi,Daisuke
2024-07-08  3:05 ` [PATCH v14 0/2] Export cxl1.1 device link status register value to pci device sysfs Daisuke Kobayashi (Fujitsu)
2024-07-08 16:23   ` Dave Jiang
2024-07-09  8:00     ` Daisuke Kobayashi (Fujitsu)

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