From: Alejandro Lucero Palau <alucerop@amd.com>
To: "Cheatham, Benjamin" <benjamin.cheatham@amd.com>,
alejandro.lucero-palau@amd.com, linux-cxl@vger.kernel.org,
djbw@kernel.org, edward.cree@amd.com, davem@davemloft.net,
kuba@kernel.org, pabeni@redhat.com, edumazet@google.com,
dave.jiang@intel.com
Cc: Jonathan Cameron <Jonathan.Cameron@huawei.com>,
Edward Cree <ecree.xilinx@gmail.com>,
Alison Schofield <alison.schofield@intel.com>,
Dan Williams <dan.j.williams@intel.com>
Subject: Re: [PATCH v26 1/8] sfc: add cxl support
Date: Fri, 1 May 2026 11:07:05 +0100 [thread overview]
Message-ID: <41219a9e-6876-42eb-ac18-3b4b7495e6e4@amd.com> (raw)
In-Reply-To: <85abaa2c-7fb2-4963-9909-74ded20c2f0f@amd.com>
On 4/29/26 22:14, Cheatham, Benjamin wrote:
> On 4/23/2026 1:05 PM, alejandro.lucero-palau@amd.com wrote:
>> From: Alejandro Lucero <alucerop@amd.com>
>>
>> Add CXL initialization based on new CXL API for accel drivers and make
>> it dependent on kernel CXL configuration.
>>
>> Signed-off-by: Alejandro Lucero <alucerop@amd.com>
>> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
>> Acked-by: Edward Cree <ecree.xilinx@gmail.com>
>> Reviewed-by: Alison Schofield <alison.schofield@intel.com>
>> Reviewed-by: Dan Williams <dan.j.williams@intel.com>
>> Reviewed-by: Dave Jiang <dave.jiang@intel.com>
> Code looks good, just some notes on the copyright notices and a tiny nit. With the copyright fixed:
>
> Reviewed-by: Ben Cheatham <benjamin.cheatham@amd.com>
Thanks. I'll fix those minor issues.
>
> [snip]
>
>> diff --git a/drivers/net/ethernet/sfc/efx_cxl.c b/drivers/net/ethernet/sfc/efx_cxl.c
>> new file mode 100644
>> index 000000000000..b7e8d85a43d3
>> --- /dev/null
>> +++ b/drivers/net/ethernet/sfc/efx_cxl.c
>> @@ -0,0 +1,52 @@
>> +// SPDX-License-Identifier: GPL-2.0-only
>> +/****************************************************************************
>> + *
>> + * Driver for AMD network controllers and boards
>> + * Copyright (C) 2025, Advanced Micro Devices, Inc.
> I'm not a lawyer, but I'm pretty sure the year needs to be 2026 here.
>> + */
>> +
>> +#include <linux/pci.h>
>> +
>> +#include "net_driver.h"
>> +#include "efx_cxl.h"
>> +
>> +#define EFX_CTPIO_BUFFER_SIZE SZ_256M
>> +
>> +int efx_cxl_init(struct efx_probe_data *probe_data)
>> +{
>> + struct efx_nic *efx = &probe_data->efx;
>> + struct pci_dev *pci_dev = efx->pci_dev;
>> + struct efx_cxl *cxl;
>> + u16 dvsec;
>> +
>> + probe_data->cxl_pio_initialised = false;
>> +
>> + /* Is the device configured with and using CXL? */
>> + if (!pcie_is_cxl(pci_dev))
>> + return 0;
>> +
>> + dvsec = pci_find_dvsec_capability(pci_dev, PCI_VENDOR_ID_CXL,
>> + PCI_DVSEC_CXL_DEVICE);
>> + if (!dvsec) {
>> + pci_info(pci_dev, "CXL_DVSEC_PCIE_DEVICE capability not found\n");
>> + return 0;
>> + }
>> +
>> + pci_dbg(pci_dev, "CXL_DVSEC_PCIE_DEVICE capability found\n");
>> +
>> + /* Create a cxl_dev_state embedded in the cxl struct using cxl core api
>> + * specifying no mbox available.
>> + */
>> + cxl = devm_cxl_dev_state_create(&pci_dev->dev, CXL_DEVTYPE_DEVMEM,
>> + pci_get_dsn(pci_dev), dvsec,
>> + struct efx_cxl, cxlds, false);
>> +
>> + if (!cxl)
>> + return -ENOMEM;
>> +
>> + probe_data->cxl = cxl;
>> +
>> + return 0;
>> +}
>> +
>> +MODULE_IMPORT_NS("CXL");
>> diff --git a/drivers/net/ethernet/sfc/efx_cxl.h b/drivers/net/ethernet/sfc/efx_cxl.h
>> new file mode 100644
>> index 000000000000..04e46278464d
>> --- /dev/null
>> +++ b/drivers/net/ethernet/sfc/efx_cxl.h
>> @@ -0,0 +1,29 @@
>> +/* SPDX-License-Identifier: GPL-2.0-only */
>> +/****************************************************************************
>> + * Driver for AMD network controllers and boards
>> + * Copyright (C) 2025, Advanced Micro Devices, Inc.
> Same thing here.
>
>> + *
>> + * This program is free software; you can redistribute it and/or modify it
>> + * under the terms of the GNU General Public License version 2 as published
>> + * by the Free Software Foundation, incorporated herein by reference.
>> + */
>> +
>> +#ifndef EFX_CXL_H
>> +#define EFX_CXL_H
>> +
>> +#ifdef CONFIG_SFC_CXL
>> +
>> +#include <cxl/cxl.h>
>> +
>> +struct efx_probe_data;
>> +
>> +struct efx_cxl {
>> + struct cxl_dev_state cxlds;
>> + struct cxl_memdev *cxlmd;
>> +};
>> +
>> +int efx_cxl_init(struct efx_probe_data *probe_data);
>> +#else
>> +static inline int efx_cxl_init(struct efx_probe_data *probe_data) { return 0; }
>> +#endif
>> +#endif
>> diff --git a/drivers/net/ethernet/sfc/net_driver.h b/drivers/net/ethernet/sfc/net_driver.h
>> index b98c259f672d..3964b2c56609 100644
>> --- a/drivers/net/ethernet/sfc/net_driver.h
>> +++ b/drivers/net/ethernet/sfc/net_driver.h
>> @@ -1197,14 +1197,24 @@ struct efx_nic {
>> atomic_t n_rx_noskb_drops;
>> };
>>
>> +#ifdef CONFIG_SFC_CXL
>> +struct efx_cxl;
>> +#endif
>> +
>> /**
>> * struct efx_probe_data - State after hardware probe
>> * @pci_dev: The PCI device
>> * @efx: Efx NIC details
>> + * @cxl: details of related cxl objects
>> + * @cxl_pio_initialised: cxl initialization outcome.
> Tiny nit: The description of the variable should use the english spelling as well (i.e. initialisation).
>
>> */
>> struct efx_probe_data {
>> struct pci_dev *pci_dev;
>> struct efx_nic efx;
>> +#ifdef CONFIG_SFC_CXL
>> + struct efx_cxl *cxl;
>> + bool cxl_pio_initialised;
>> +#endif
>> };
>>
>> static inline struct efx_nic *efx_netdev_priv(struct net_device *dev)
next prev parent reply other threads:[~2026-05-01 10:07 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-04-23 18:05 [PATCH v26 0/8] Type2 device basic support alejandro.lucero-palau
2026-04-23 18:05 ` [PATCH v26 1/8] sfc: add cxl support alejandro.lucero-palau
2026-04-29 21:14 ` Cheatham, Benjamin
2026-05-01 10:07 ` Alejandro Lucero Palau [this message]
2026-04-23 18:05 ` [PATCH v26 2/8] cxl/sfc: Map cxl regs alejandro.lucero-palau
2026-04-23 18:05 ` [PATCH v26 3/8] cxl/sfc: Initialize dpa without a mailbox alejandro.lucero-palau
2026-04-23 18:05 ` [PATCH v26 4/8] cxl: Prepare memdev creation for type2 alejandro.lucero-palau
2026-04-30 23:23 ` Dan Williams (nvidia)
2026-04-23 18:05 ` [PATCH v26 5/8] sfc: create type2 cxl memdev alejandro.lucero-palau
2026-04-23 18:05 ` [PATCH v26 6/8] cxl: attach region to an accelerator/type2 memdev alejandro.lucero-palau
2026-04-29 21:14 ` Cheatham, Benjamin
2026-05-01 10:35 ` Alejandro Lucero Palau
2026-05-01 2:00 ` Dan Williams (nvidia)
2026-05-01 10:59 ` Alejandro Lucero Palau
2026-05-02 0:46 ` Dan Williams (nvidia)
2026-05-05 20:51 ` Alejandro Lucero Palau
2026-04-23 18:05 ` [PATCH v26 7/8] cxl: Avoid dax creation for accelerators alejandro.lucero-palau
2026-04-29 21:14 ` Cheatham, Benjamin
2026-04-23 18:05 ` [PATCH v26 8/8] sfc: support pio mapping based on cxl alejandro.lucero-palau
2026-04-23 22:07 ` [PATCH v26 0/8] Type2 device basic support Dave Jiang
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