From: Dave Jiang <dave.jiang@intel.com>
To: Jonathan Cameron <Jonathan.Cameron@Huawei.com>
Cc: <linux-cxl@vger.kernel.org>,
Dan Williams <dan.j.williams@intel.com>, <ira.weiny@intel.com>,
<vishal.l.verma@intel.com>, <alison.schofield@intel.com>,
<dave@stgolabs.net>
Subject: Re: [PATCH v10 21/22] cxl: Export sysfs attributes for memory device QoS class
Date: Wed, 11 Oct 2023 14:43:14 -0700 [thread overview]
Message-ID: <48be28cb-ed68-45c4-a271-bf9492c75eb4@intel.com> (raw)
In-Reply-To: <20231011142626.00002b16@Huawei.com>
On 10/11/23 06:26, Jonathan Cameron wrote:
> On Tue, 10 Oct 2023 18:07:06 -0700
> Dave Jiang <dave.jiang@intel.com> wrote:
>
>> Export qos_class sysfs attributes for the CXL memory device. The QoS clas
>> should show up as /sys/bus/cxl/devices/memX/ram/qos_class0 for the volatile
>> partition and /sys/bus/cxl/devices/memX/pmem/qos_class0 for the persistent
>> partition. The QTG ID is retrieved via _DSM after supplying the
>> calculated bandwidth and latency for the entire CXL path from device to
>> the CPU. This ID is used to match up to the root decoder QoS class to
>> determine which CFMWS the memory range of a hotplugged CXL mem device
>> should be assigned under.
>>
>> While there may be multiple DSMAS exported by the device CDAT, the driver
>> will only expose the first QTG ID per partition in sysfs for now. In the
>> future when multiple QTG IDs are necessary, they can be exposed. [1]
>
> I'm not sure this will extent cleanly if we get a two dimensional set to describle
> 1) Multiple DSMAS entries for RAM (so multiple inputs to pass to the _DSM)
> One nice thing here might be to ensure we have the first one seen.
> So if in future we do need to extent it this corresponds to the 0th one
> described.
> 2) Want to describe less ideal QTG values from _DSM
>
>
> Maybe it's too early to come to any conclusion and the single 0 is enough.
> The cynic in me suggests we call it. qos_class0_0 though to give us the space.
> If we needs DSMAS ranges, then we describe those using first index,
> and second is the priority index if we have multiple answers from _DSM.
> For now it's always 0_0
I talked to Dan and it seems he prefers the simplest form for the current version until we have a need to move towards something more complex. So qos_class0 -> qos_class. We can move to qos_classN_M when there is a need.
>
>
> Jonathan
>
>>
>> [1]: https://lore.kernel.org/linux-cxl/167571650007.587790.10040913293130712882.stgit@djiang5-mobl3.local/T/#md2a47b1ead3e1ba08f50eab29a4af1aed1d215ab
>>
>> Suggested-by: Dan Williams <dan.j.williams@intel.com>
>> Signed-off-by: Dave Jiang <dave.jiang@intel.com>
>>
>> ---
>> v10:
>> - Export only qos_class0, the first entry. Additional qos_class entries can be
>> exported later as needed. (Dan)
>> - Have the sysfs attrib return -ENOENT unless driver is attached. (Dan)
>> - Removed Jonathan's review tag due to code changes.
>> ---
>> Documentation/ABI/testing/sysfs-bus-cxl | 34 +++++++++++++++++++++++++++++++
>> drivers/cxl/core/memdev.c | 34 +++++++++++++++++++++++++++++++
>> 2 files changed, 68 insertions(+)
>>
>> diff --git a/Documentation/ABI/testing/sysfs-bus-cxl b/Documentation/ABI/testing/sysfs-bus-cxl
>> index 44ffbbb36654..dd613f5987b5 100644
>> --- a/Documentation/ABI/testing/sysfs-bus-cxl
>> +++ b/Documentation/ABI/testing/sysfs-bus-cxl
>> @@ -28,6 +28,23 @@ Description:
>> Payload in the CXL-2.0 specification.
>>
>>
>> +What: /sys/bus/cxl/devices/memX/ram/qos_class0
>> +Date: May, 2023
>> +KernelVersion: v6.7
>> +Contact: linux-cxl@vger.kernel.org
>> +Description:
>> + (RO) For CXL host platforms that support "QoS Telemmetry"
>> + this attribute conveys a comma delimited list of platform
>> + specific cookies that identifies a QoS performance class
>> + for the volatile partition of the CXL mem device. These
>> + class-ids can be compared against a similar "qos_class"
>> + published for a root decoder. While it is not required
>> + that the endpoints map their local memory-class to a
>> + matching platform class, mismatches are not recommended
>> + and there are platform specific performance related
>> + side-effects that may result. First class-id is displayed.
>> +
>> +
>> What: /sys/bus/cxl/devices/memX/pmem/size
>> Date: December, 2020
>> KernelVersion: v5.12
>> @@ -38,6 +55,23 @@ Description:
>> Payload in the CXL-2.0 specification.
>>
>>
>> +What: /sys/bus/cxl/devices/memX/pmem/qos_class0
>> +Date: May, 2023
>> +KernelVersion: v6.7
>> +Contact: linux-cxl@vger.kernel.org
>> +Description:
>> + (RO) For CXL host platforms that support "QoS Telemmetry"
>> + this attribute conveys a comma delimited list of platform
>> + specific cookies that identifies a QoS performance class
>> + for the persistent partition of the CXL mem device. These
>> + class-ids can be compared against a similar "qos_class"
>> + published for a root decoder. While it is not required
>> + that the endpoints map their local memory-class to a
>> + matching platform class, mismatches are not recommended
>> + and there are platform specific performance related
>> + side-effects that may result. First class-id is displayed.
>> +
>> +
>
>
next prev parent reply other threads:[~2023-10-11 21:43 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-11 1:04 [PATCH v10 00/22] cxl: Add support for QTG ID retrieval for CXL subsystem Dave Jiang
2023-10-11 1:05 ` [PATCH v10 01/22] cxl: Export QTG ids from CFMWS to sysfs as qos_class attribute Dave Jiang
2023-10-11 1:05 ` [PATCH v10 02/22] cxl: Add checksum verification to CDAT from CXL Dave Jiang
2023-10-11 1:05 ` [PATCH v10 03/22] cxl: Add support for reading CXL switch CDAT table Dave Jiang
2023-10-11 1:05 ` [PATCH v10 04/22] acpi: Move common tables helper functions to common lib Dave Jiang
2023-10-11 12:55 ` Jonathan Cameron
2023-10-11 1:05 ` [PATCH v10 05/22] lib/firmware_table: tables: Add CDAT table parsing support Dave Jiang
2023-10-11 1:05 ` [PATCH v10 06/22] base/node / acpi: Change 'node_hmem_attrs' to 'access_coordinates' Dave Jiang
2023-10-11 12:57 ` Jonathan Cameron
2023-10-11 1:05 ` [PATCH v10 07/22] acpi: numa: Create enum for memory_target access coordinates indexing Dave Jiang
2023-10-11 1:05 ` [PATCH v10 08/22] acpi: numa: Add genport target allocation to the HMAT parsing Dave Jiang
2023-10-11 1:05 ` [PATCH v10 09/22] acpi: Break out nesting for hmat_parse_locality() Dave Jiang
2023-10-11 1:05 ` [PATCH v10 10/22] acpi: numa: Add setting of generic port system locality attributes Dave Jiang
2023-10-11 1:06 ` [PATCH v10 11/22] acpi: numa: Add helper function to retrieve the performance attributes Dave Jiang
2023-10-11 1:06 ` [PATCH v10 12/22] cxl: Add callback to parse the DSMAS subtables from CDAT Dave Jiang
2023-10-11 1:06 ` [PATCH v10 13/22] cxl: Add callback to parse the DSLBIS subtable " Dave Jiang
2023-10-11 1:06 ` [PATCH v10 14/22] cxl: Add callback to parse the SSLBIS " Dave Jiang
2023-10-11 1:06 ` [PATCH v10 15/22] cxl: Add support for _DSM Function for retrieving QTG ID Dave Jiang
2023-10-11 13:10 ` Jonathan Cameron
2023-10-11 15:37 ` Dave Jiang
2023-10-11 1:06 ` [PATCH v10 16/22] cxl: Calculate and store PCI link latency for the downstream ports Dave Jiang
2023-10-11 1:06 ` [PATCH v10 17/22] cxl: Store the access coordinates for the generic ports Dave Jiang
2023-10-11 1:06 ` [PATCH v10 18/22] cxl: Add helper function that calculate performance data for downstream ports Dave Jiang
2023-10-11 1:06 ` [PATCH v10 19/22] cxl: Compute the entire CXL path latency and bandwidth data Dave Jiang
2023-10-11 1:06 ` [PATCH v10 20/22] cxl: Store QTG IDs and related info to the CXL memory device context Dave Jiang
2023-10-11 13:19 ` Jonathan Cameron
2023-10-11 16:04 ` Dave Jiang
2023-10-11 1:07 ` [PATCH v10 21/22] cxl: Export sysfs attributes for memory device QoS class Dave Jiang
2023-10-11 13:26 ` Jonathan Cameron
2023-10-11 21:43 ` Dave Jiang [this message]
2023-10-12 11:04 ` Jonathan Cameron
2023-10-11 1:07 ` [PATCH v10 22/22] cxl: Check qos_class validity on memdev probe Dave Jiang
2023-10-11 13:29 ` Jonathan Cameron
2023-10-11 16:28 ` Dave Jiang
2023-10-11 12:59 ` [PATCH v10 00/22] cxl: Add support for QTG ID retrieval for CXL subsystem Jonathan Cameron
2023-10-11 16:31 ` Dave Jiang
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