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From: Dave Jiang <dave.jiang@intel.com>
To: Jonathan Cameron <Jonathan.Cameron@Huawei.com>
Cc: <linux-cxl@vger.kernel.org>, <dan.j.williams@intel.com>,
	<ira.weiny@intel.com>, <vishal.l.verma@intel.com>,
	<alison.schofield@intel.com>, <dave@stgolabs.net>
Subject: Re: [PATCH v10 22/22] cxl: Check qos_class validity on memdev probe
Date: Wed, 11 Oct 2023 09:28:33 -0700	[thread overview]
Message-ID: <fd0082bf-7229-4767-bebb-ef318596ea52@intel.com> (raw)
In-Reply-To: <20231011142924.00006060@Huawei.com>



On 10/11/23 06:29, Jonathan Cameron wrote:
> On Tue, 10 Oct 2023 18:07:11 -0700
> Dave Jiang <dave.jiang@intel.com> wrote:
> 
>> Add a check to make sure the qos_class for the device will match one of
>> the root decoders qos_class. If no match is found, then the qos_class for
>> the device is set to invalid.
>>
>> Signed-off-by: Dave Jiang <dave.jiang@intel.com>
>> ---
>>  drivers/cxl/mem.c |   68 +++++++++++++++++++++++++++++++++++++++++++++++++++++
>>  1 file changed, 68 insertions(+)
>>
>> diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c
>> index 317c7548e4e9..3495119d2edf 100644
>> --- a/drivers/cxl/mem.c
>> +++ b/drivers/cxl/mem.c
>> @@ -104,6 +104,70 @@ static int cxl_debugfs_poison_clear(void *data, u64 dpa)
>>  DEFINE_DEBUGFS_ATTRIBUTE(cxl_poison_clear_fops, NULL,
>>  			 cxl_debugfs_poison_clear, "%llx\n");
>>  
>> +struct qos_class_ctx {
>> +	bool matched;
>> +	int dev_qos_class;
>> +};
>> +
>> +static int match_cxlrd_qos_class(struct device *dev, void *data)
>> +{
>> +	struct qos_class_ctx *ctx = data;
>> +	struct cxl_root_decoder *cxlrd;
>> +
>> +	if (ctx->matched)
>> +		return 0;
>> +
>> +	if (!is_root_decoder(dev))
>> +		return 0;
>> +
>> +	cxlrd = to_cxl_root_decoder(dev);
>> +	if (cxlrd->qos_class == CXL_QOS_CLASS_INVALID ||
>> +	    ctx->dev_qos_class == CXL_QOS_CLASS_INVALID)
>> +		return 0;
>> +
>> +	if (cxlrd->qos_class == ctx->dev_qos_class)
>> +		ctx->matched = 1;
> If matched, why not terminate the bus_for_each_dev()
> That is return 1 and amend check to be if (rc < 0)
> Not that this ever returns < 0 anyway.  It might in
> future though so that test makes sense as defensive measure.

Will update.

> 
> 
>> +
>> +	return 0;
>> +}
>> +
>> +static int cxl_qos_class_verify(struct cxl_memdev *cxlmd)
>> +{
>> +	struct device *dev = &cxlmd->dev;
>> +	struct cxl_dev_state *cxlds = cxlmd->cxlds;
>> +	struct cxl_memdev_state *mds = to_cxl_memdev_state(cxlds);
>> +	struct qos_class_ctx ctx;
>> +	int rc;
>> +
>> +	if (mds->ram_qos_class != CXL_QOS_CLASS_INVALID) {
>> +		ctx.matched = false;
>> +		ctx.dev_qos_class =  mds->ram_qos_class;
>> +		rc = bus_for_each_dev(dev->bus, NULL, &ctx, match_cxlrd_qos_class);
>> +		if (rc)
>> +			return rc;
>> +
>> +		if (ctx.matched)
>> +			return 0;
> Early return doesn't make sense to me given not checked the pmem one yet.

You are right. Will fix.

>> +
>> +		mds->ram_qos_class = CXL_QOS_CLASS_INVALID;
>> +	}
>> +
>> +	if (mds->pmem_qos_class != CXL_QOS_CLASS_INVALID) {
>> +		ctx.matched = false;
>> +		ctx.dev_qos_class = mds->pmem_qos_class;
>> +		rc = bus_for_each_dev(dev->bus, NULL, &ctx, match_cxlrd_qos_class);
>> +		if (rc)
>> +			return rc;
>> +
>> +		if (ctx.matched)
>> +			return 0;
>> +
>> +		mds->ram_qos_class = CXL_QOS_CLASS_INVALID;
> 
> pmem_qos_class?

copy/paste error. will fix.

> 
>> +	}
>> +
>> +	return 0;
>> +}
>> +
>>  static int cxl_mem_probe(struct device *dev)
>>  {
>>  	struct cxl_memdev *cxlmd = to_cxl_memdev(dev);
>> @@ -181,6 +245,10 @@ static int cxl_mem_probe(struct device *dev)
>>  			return rc;
>>  	}
>>  
>> +	rc = cxl_qos_class_verify(cxlmd);
>> +	if (rc)
>> +		return rc;
>> +
>>  	/*
>>  	 * The kernel may be operating out of CXL memory on this device,
>>  	 * there is no spec defined way to determine whether this device
>>
>>
> 

  reply	other threads:[~2023-10-11 16:29 UTC|newest]

Thread overview: 36+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-10-11  1:04 [PATCH v10 00/22] cxl: Add support for QTG ID retrieval for CXL subsystem Dave Jiang
2023-10-11  1:05 ` [PATCH v10 01/22] cxl: Export QTG ids from CFMWS to sysfs as qos_class attribute Dave Jiang
2023-10-11  1:05 ` [PATCH v10 02/22] cxl: Add checksum verification to CDAT from CXL Dave Jiang
2023-10-11  1:05 ` [PATCH v10 03/22] cxl: Add support for reading CXL switch CDAT table Dave Jiang
2023-10-11  1:05 ` [PATCH v10 04/22] acpi: Move common tables helper functions to common lib Dave Jiang
2023-10-11 12:55   ` Jonathan Cameron
2023-10-11  1:05 ` [PATCH v10 05/22] lib/firmware_table: tables: Add CDAT table parsing support Dave Jiang
2023-10-11  1:05 ` [PATCH v10 06/22] base/node / acpi: Change 'node_hmem_attrs' to 'access_coordinates' Dave Jiang
2023-10-11 12:57   ` Jonathan Cameron
2023-10-11  1:05 ` [PATCH v10 07/22] acpi: numa: Create enum for memory_target access coordinates indexing Dave Jiang
2023-10-11  1:05 ` [PATCH v10 08/22] acpi: numa: Add genport target allocation to the HMAT parsing Dave Jiang
2023-10-11  1:05 ` [PATCH v10 09/22] acpi: Break out nesting for hmat_parse_locality() Dave Jiang
2023-10-11  1:05 ` [PATCH v10 10/22] acpi: numa: Add setting of generic port system locality attributes Dave Jiang
2023-10-11  1:06 ` [PATCH v10 11/22] acpi: numa: Add helper function to retrieve the performance attributes Dave Jiang
2023-10-11  1:06 ` [PATCH v10 12/22] cxl: Add callback to parse the DSMAS subtables from CDAT Dave Jiang
2023-10-11  1:06 ` [PATCH v10 13/22] cxl: Add callback to parse the DSLBIS subtable " Dave Jiang
2023-10-11  1:06 ` [PATCH v10 14/22] cxl: Add callback to parse the SSLBIS " Dave Jiang
2023-10-11  1:06 ` [PATCH v10 15/22] cxl: Add support for _DSM Function for retrieving QTG ID Dave Jiang
2023-10-11 13:10   ` Jonathan Cameron
2023-10-11 15:37     ` Dave Jiang
2023-10-11  1:06 ` [PATCH v10 16/22] cxl: Calculate and store PCI link latency for the downstream ports Dave Jiang
2023-10-11  1:06 ` [PATCH v10 17/22] cxl: Store the access coordinates for the generic ports Dave Jiang
2023-10-11  1:06 ` [PATCH v10 18/22] cxl: Add helper function that calculate performance data for downstream ports Dave Jiang
2023-10-11  1:06 ` [PATCH v10 19/22] cxl: Compute the entire CXL path latency and bandwidth data Dave Jiang
2023-10-11  1:06 ` [PATCH v10 20/22] cxl: Store QTG IDs and related info to the CXL memory device context Dave Jiang
2023-10-11 13:19   ` Jonathan Cameron
2023-10-11 16:04     ` Dave Jiang
2023-10-11  1:07 ` [PATCH v10 21/22] cxl: Export sysfs attributes for memory device QoS class Dave Jiang
2023-10-11 13:26   ` Jonathan Cameron
2023-10-11 21:43     ` Dave Jiang
2023-10-12 11:04       ` Jonathan Cameron
2023-10-11  1:07 ` [PATCH v10 22/22] cxl: Check qos_class validity on memdev probe Dave Jiang
2023-10-11 13:29   ` Jonathan Cameron
2023-10-11 16:28     ` Dave Jiang [this message]
2023-10-11 12:59 ` [PATCH v10 00/22] cxl: Add support for QTG ID retrieval for CXL subsystem Jonathan Cameron
2023-10-11 16:31   ` Dave Jiang

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