From: Dave Jiang <dave.jiang@intel.com>
To: Zhi Wang <zhiw@nvidia.com>
Cc: alejandro.lucero-palau@amd.com, linux-cxl@vger.kernel.org,
netdev@vger.kernel.org, dan.j.williams@intel.com,
martin.habets@xilinx.com, edward.cree@amd.com,
davem@davemloft.net, kuba@kernel.org, pabeni@redhat.com,
edumazet@google.com, Alejandro Lucero <alucerop@amd.com>
Subject: Re: [PATCH v5 13/27] cxl: prepare memdev creation for type2
Date: Tue, 19 Nov 2024 14:27:41 -0700 [thread overview]
Message-ID: <4fc8fd99-f349-47f9-8f5e-d4c393370ada@intel.com> (raw)
In-Reply-To: <20241119220605.00005808@nvidia.com>
On 11/19/24 1:06 PM, Zhi Wang wrote:
> On Tue, 19 Nov 2024 11:24:44 -0700
> Dave Jiang <dave.jiang@intel.com> wrote:
>
>>
>>
>> On 11/18/24 9:44 AM, alejandro.lucero-palau@amd.com wrote:
>>> From: Alejandro Lucero <alucerop@amd.com>
>>>
>>> Current cxl core is relying on a CXL_DEVTYPE_CLASSMEM type device
>>> when creating a memdev leading to problems when obtaining
>>> cxl_memdev_state references from a CXL_DEVTYPE_DEVMEM type. This
>>> last device type is managed by a specific vendor driver and does
>>> not need same sysfs files since not userspace intervention is
>>> expected.
>>>
>>> Create a new cxl_mem device type with no attributes for Type2.
>>>
>>> Avoid debugfs files relying on existence of clx_memdev_state.
>>>
>>> Make devm_cxl_add_memdev accesible from a accel driver.
>>>
>>> Signed-off-by: Alejandro Lucero <alucerop@amd.com>
>>> ---
>>> drivers/cxl/core/cdat.c | 3 +++
>>> drivers/cxl/core/memdev.c | 15 +++++++++++++--
>>> drivers/cxl/core/region.c | 3 ++-
>>> drivers/cxl/mem.c | 25 +++++++++++++++++++------
>>> include/cxl/cxl.h | 2 ++
>>> 5 files changed, 39 insertions(+), 9 deletions(-)
>>>
>>> diff --git a/drivers/cxl/core/cdat.c b/drivers/cxl/core/cdat.c
>>> index e9cd7939c407..192cff18ea25 100644
>>> --- a/drivers/cxl/core/cdat.c
>>> +++ b/drivers/cxl/core/cdat.c
>>> @@ -577,6 +577,9 @@ static struct cxl_dpa_perf
>>> *cxled_get_dpa_perf(struct cxl_endpoint_decoder *cxle struct
>>> cxl_memdev_state *mds = to_cxl_memdev_state(cxlmd->cxlds); struct
>>> cxl_dpa_perf *perf;
>>> + if (!mds)
>>> + return ERR_PTR(-EINVAL);
>>> +
>>> switch (mode) {
>>> case CXL_DECODER_RAM:
>>> perf = &mds->ram_perf;
>>> diff --git a/drivers/cxl/core/memdev.c b/drivers/cxl/core/memdev.c
>>> index d746c8a1021c..df31eea0c06b 100644
>>> --- a/drivers/cxl/core/memdev.c
>>> +++ b/drivers/cxl/core/memdev.c
>>> @@ -547,9 +547,17 @@ static const struct device_type
>>> cxl_memdev_type = { .groups = cxl_memdev_attribute_groups,
>>> };
>>>
>>> +static const struct device_type cxl_accel_memdev_type = {
>>> + .name = "cxl_memdev",
>>> + .release = cxl_memdev_release,
>>> + .devnode = cxl_memdev_devnode,
>>> +};
>>> +
>>> bool is_cxl_memdev(const struct device *dev)
>>> {
>>> - return dev->type == &cxl_memdev_type;
>>> + return (dev->type == &cxl_memdev_type ||
>>> + dev->type == &cxl_accel_memdev_type);
>>> +
>>> }
>>> EXPORT_SYMBOL_NS_GPL(is_cxl_memdev, CXL);
>>
>> Does type2 device also exports a CDAT?
>>
>
> Yes. Type2 can also export a CDAT.
Thanks! Probably should have the split out helpers regardless.
>
>> I'm also wondering if we should have distinctive helpers:
>> is_cxl_type3_memdev()
>> is_cxl_type2_memdev()
>>
>> and is_cxl_memdev() is just calling those two helpers above.
>>
>> And if no CDAT is exported, we should change the is_cxl_memdev() to
>> is_cxl_type3_memdev() in read_cdat_data().
>>
>> DJ
>>
>>>
>>> @@ -660,7 +668,10 @@ static struct cxl_memdev
>>> *cxl_memdev_alloc(struct cxl_dev_state *cxlds, dev->parent =
>>> cxlds->dev; dev->bus = &cxl_bus_type;
>>> dev->devt = MKDEV(cxl_mem_major, cxlmd->id);
>>> - dev->type = &cxl_memdev_type;
>>> + if (cxlds->type == CXL_DEVTYPE_DEVMEM)
>>> + dev->type = &cxl_accel_memdev_type;
>>> + else
>>> + dev->type = &cxl_memdev_type;
>>> device_set_pm_not_required(dev);
>>> INIT_WORK(&cxlmd->detach_work, detach_memdev);
>>>
>>> diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c
>>> index dff618c708dc..622e3bb2e04b 100644
>>> --- a/drivers/cxl/core/region.c
>>> +++ b/drivers/cxl/core/region.c
>>> @@ -1948,7 +1948,8 @@ static int cxl_region_attach(struct
>>> cxl_region *cxlr, return -EINVAL;
>>> }
>>>
>>> - cxl_region_perf_data_calculate(cxlr, cxled);
>>> + if (cxlr->type == CXL_DECODER_HOSTONLYMEM)
>>> + cxl_region_perf_data_calculate(cxlr, cxled);
>>>
>>> if (test_bit(CXL_REGION_F_AUTO, &cxlr->flags)) {
>>> int i;
>>> diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c
>>> index a9fd5cd5a0d2..cb771bf196cd 100644
>>> --- a/drivers/cxl/mem.c
>>> +++ b/drivers/cxl/mem.c
>>> @@ -130,12 +130,18 @@ static int cxl_mem_probe(struct device *dev)
>>> dentry = cxl_debugfs_create_dir(dev_name(dev));
>>> debugfs_create_devm_seqfile(dev, "dpamem", dentry,
>>> cxl_mem_dpa_show);
>>> - if (test_bit(CXL_POISON_ENABLED_INJECT,
>>> mds->poison.enabled_cmds))
>>> - debugfs_create_file("inject_poison", 0200, dentry,
>>> cxlmd,
>>> - &cxl_poison_inject_fops);
>>> - if (test_bit(CXL_POISON_ENABLED_CLEAR,
>>> mds->poison.enabled_cmds))
>>> - debugfs_create_file("clear_poison", 0200, dentry,
>>> cxlmd,
>>> - &cxl_poison_clear_fops);
>>> + /*
>>> + * Avoid poison debugfs files for Type2 devices as they
>>> rely on
>>> + * cxl_memdev_state.
>>> + */
>>> + if (mds) {
>>> + if (test_bit(CXL_POISON_ENABLED_INJECT,
>>> mds->poison.enabled_cmds))
>>> + debugfs_create_file("inject_poison", 0200,
>>> dentry, cxlmd,
>>> +
>>> &cxl_poison_inject_fops);
>>> + if (test_bit(CXL_POISON_ENABLED_CLEAR,
>>> mds->poison.enabled_cmds))
>>> + debugfs_create_file("clear_poison", 0200,
>>> dentry, cxlmd,
>>> +
>>> &cxl_poison_clear_fops);
>>> + }
>>>
>>> rc = devm_add_action_or_reset(dev, remove_debugfs, dentry);
>>> if (rc)
>>> @@ -219,6 +225,13 @@ static umode_t cxl_mem_visible(struct kobject
>>> *kobj, struct attribute *a, int n) struct cxl_memdev *cxlmd =
>>> to_cxl_memdev(dev); struct cxl_memdev_state *mds =
>>> to_cxl_memdev_state(cxlmd->cxlds);
>>> + /*
>>> + * Avoid poison sysfs files for Type2 devices as they rely
>>> on
>>> + * cxl_memdev_state.
>>> + */
>>> + if (!mds)
>>> + return 0;
>>> +
>>> if (a == &dev_attr_trigger_poison_list.attr)
>>> if (!test_bit(CXL_POISON_ENABLED_LIST,
>>> mds->poison.enabled_cmds))
>>> diff --git a/include/cxl/cxl.h b/include/cxl/cxl.h
>>> index 6033ce84b3d3..5608ed0f5f15 100644
>>> --- a/include/cxl/cxl.h
>>> +++ b/include/cxl/cxl.h
>>> @@ -57,4 +57,6 @@ int cxl_pci_accel_setup_regs(struct pci_dev
>>> *pdev, struct cxl_dev_state *cxlds); int
>>> cxl_request_resource(struct cxl_dev_state *cxlds, enum cxl_resource
>>> type); int cxl_release_resource(struct cxl_dev_state *cxlds, enum
>>> cxl_resource type); void cxl_set_media_ready(struct cxl_dev_state
>>> *cxlds); +struct cxl_memdev *devm_cxl_add_memdev(struct device
>>> *host,
>>> + struct cxl_dev_state
>>> *cxlds); #endif
>>
>>
>
next prev parent reply other threads:[~2024-11-19 21:27 UTC|newest]
Thread overview: 99+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-11-18 16:44 [PATCH v5 00/27] cxl: add type2 device basic support alejandro.lucero-palau
2024-11-18 16:44 ` [PATCH v5 01/27] " alejandro.lucero-palau
2024-11-18 21:55 ` Dave Jiang
2024-11-20 13:40 ` Alejandro Lucero Palau
2024-11-20 23:07 ` Fan Ni
2024-11-22 4:35 ` Alison Schofield
2024-11-22 9:27 ` Alejandro Lucero Palau
2024-11-26 5:59 ` Alison Schofield
2024-11-26 16:38 ` Alejandro Lucero Palau
2024-11-22 20:43 ` Ben Cheatham
2024-11-27 9:00 ` Alejandro Lucero Palau
2024-11-27 9:07 ` Alejandro Lucero Palau
2024-11-18 16:44 ` [PATCH v5 02/27] sfc: add cxl support using new CXL API alejandro.lucero-palau
2024-11-22 20:43 ` Ben Cheatham
2024-11-27 9:15 ` Alejandro Lucero Palau
2024-11-26 18:08 ` Fan Ni
2024-11-27 9:17 ` Alejandro Lucero Palau
2024-11-18 16:44 ` [PATCH v5 03/27] cxl: add capabilities field to cxl_dev_state and cxl_port alejandro.lucero-palau
2024-11-18 22:52 ` Dave Jiang
2024-11-19 12:28 ` Alejandro Lucero Palau
2024-11-19 15:53 ` Dave Jiang
2024-11-20 13:41 ` Alejandro Lucero Palau
2024-11-22 20:44 ` Ben Cheatham
2024-11-18 16:44 ` [PATCH v5 04/27] cxl/pci: add check for validating capabilities alejandro.lucero-palau
2024-11-22 20:44 ` Ben Cheatham
2024-11-27 11:34 ` Alejandro Lucero Palau
2024-11-18 16:44 ` [PATCH v5 05/27] cxl: move pci generic code alejandro.lucero-palau
2024-11-18 22:57 ` Dave Jiang
2024-11-22 20:44 ` Ben Cheatham
2024-11-18 16:44 ` [PATCH v5 06/27] cxl: add function for type2 cxl regs setup alejandro.lucero-palau
2024-11-18 23:32 ` Dave Jiang
2024-11-21 22:34 ` Alison Schofield
2024-11-27 11:46 ` Alejandro Lucero Palau
2024-11-18 16:44 ` [PATCH v5 07/27] sfc: use cxl api for regs setup and checking alejandro.lucero-palau
2024-11-18 16:44 ` [PATCH v5 08/27] cxl: add functions for resource request/release by a driver alejandro.lucero-palau
2024-11-22 20:45 ` Ben Cheatham
2024-11-18 16:44 ` [PATCH v5 09/27] sfc: request cxl ram resource alejandro.lucero-palau
2024-11-18 16:44 ` [PATCH v5 10/27] cxl: harden resource_contains checks to handle zero size resources alejandro.lucero-palau
2024-11-19 18:00 ` Dave Jiang
2024-11-20 13:44 ` Alejandro Lucero Palau
2024-11-19 19:50 ` Zhi Wang
2024-11-20 13:45 ` Alejandro Lucero Palau
2024-11-21 7:13 ` Zhi Wang
2024-11-21 2:46 ` Alison Schofield
2024-11-21 9:22 ` Alejandro Lucero Palau
2024-11-21 21:00 ` Alison Schofield
2024-11-27 14:56 ` Alejandro Lucero Palau
2024-11-18 16:44 ` [PATCH v5 11/27] cxl: add function for setting media ready by a driver alejandro.lucero-palau
2024-11-19 18:12 ` Dave Jiang
2024-11-22 20:45 ` Ben Cheatham
2024-11-27 15:07 ` Alejandro Lucero Palau
2024-11-18 16:44 ` [PATCH v5 12/27] sfc: set cxl media ready alejandro.lucero-palau
2024-11-18 16:44 ` [PATCH v5 13/27] cxl: prepare memdev creation for type2 alejandro.lucero-palau
2024-11-19 18:24 ` Dave Jiang
2024-11-19 20:06 ` Zhi Wang
2024-11-19 21:27 ` Dave Jiang [this message]
2024-11-20 13:57 ` Alejandro Lucero Palau
2024-11-20 17:15 ` Dave Jiang
2024-11-21 7:43 ` Zhi Wang
2024-11-22 20:45 ` Ben Cheatham
2024-11-27 16:09 ` Alejandro Lucero Palau
2024-11-18 16:44 ` [PATCH v5 14/27] sfc: create type2 cxl memdev alejandro.lucero-palau
2024-11-18 16:44 ` [PATCH v5 15/27] cxl: define a driver interface for HPA free space enumeration alejandro.lucero-palau
2024-11-22 20:45 ` Ben Cheatham
2024-11-27 16:32 ` Alejandro Lucero Palau
2024-11-18 16:44 ` [PATCH v5 16/27] sfc: obtain root decoder with enough HPA free space alejandro.lucero-palau
2024-11-18 16:44 ` [PATCH v5 17/27] cxl: define a driver interface for DPA allocation alejandro.lucero-palau
2024-11-18 16:44 ` [PATCH v5 18/27] sfc: get endpoint decoder alejandro.lucero-palau
2024-11-22 20:45 ` Ben Cheatham
2024-11-27 16:47 ` Alejandro Lucero Palau
2024-11-18 16:44 ` [PATCH v5 19/27] cxl: make region type based on endpoint type alejandro.lucero-palau
2024-11-19 20:16 ` Zhi Wang
2024-11-21 16:16 ` Dave Jiang
2024-11-18 16:44 ` [PATCH v5 20/27] cxl/region: factor out interleave ways setup alejandro.lucero-palau
2024-11-19 20:20 ` Zhi Wang
2024-11-21 16:23 ` Dave Jiang
2024-11-18 16:44 ` [PATCH v5 21/27] cxl/region: factor out interleave granularity setup alejandro.lucero-palau
2024-11-19 20:23 ` Zhi Wang
2024-11-21 16:24 ` Dave Jiang
2024-11-18 16:44 ` [PATCH v5 22/27] cxl: allow region creation by type2 drivers alejandro.lucero-palau
2024-11-19 20:37 ` Zhi Wang
2024-11-20 13:51 ` Alejandro Lucero Palau
2024-11-18 16:44 ` [PATCH v5 23/27] sfc: create cxl region alejandro.lucero-palau
2024-11-18 16:44 ` [PATCH v5 24/27] cxl: add region flag for precluding a device memory to be used for dax alejandro.lucero-palau
2024-11-19 20:39 ` Zhi Wang
2024-11-20 13:55 ` Alejandro Lucero Palau
2024-11-22 20:46 ` Ben Cheatham
2024-11-27 16:59 ` Alejandro Lucero Palau
2024-11-18 16:44 ` [PATCH v5 25/27] sfc: specify avoid dax when cxl region is created alejandro.lucero-palau
2024-11-18 16:44 ` [PATCH v5 26/27] cxl: add function for obtaining params from a region alejandro.lucero-palau
2024-11-19 20:40 ` Zhi Wang
2024-11-21 2:56 ` Alison Schofield
2024-11-27 17:18 ` Alejandro Lucero Palau
2024-11-21 16:31 ` Dave Jiang
2024-11-27 17:12 ` Alejandro Lucero Palau
2024-11-18 16:44 ` [PATCH v5 27/27] sfc: support pio mapping based on cxl alejandro.lucero-palau
2024-11-21 3:33 ` [PATCH v5 00/27] cxl: add type2 device basic support Alison Schofield
2024-11-21 9:27 ` Alejandro Lucero Palau
2024-11-22 4:14 ` Alison Schofield
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