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From: Dan Williams <dan.j.williams@intel.com>
To: Terry Bowman <terry.bowman@amd.com>, <alison.schofield@intel.com>,
	<vishal.l.verma@intel.com>, <dave.jiang@intel.com>,
	<ira.weiny@intel.com>, <bwidawsk@kernel.org>,
	<dan.j.williams@intel.com>
Cc: <terry.bowman@amd.com>, <linux-cxl@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>, <bhelgaas@google.com>,
	<rafael@kernel.org>, <lenb@kernel.org>,
	<Jonathan.Cameron@huawei.com>, <dave@stgolabs.net>,
	<rrichter@amd.com>, <linux-acpi@vger.kernel.org>
Subject: RE: [PATCH 1/5] cxl/acpi: Set ACPI's CXL _OSC to indicate CXL1.1 support
Date: Fri, 21 Oct 2022 15:39:41 -0700	[thread overview]
Message-ID: <63531fad96dcd_6be129496@dwillia2-xfh.jf.intel.com.notmuch> (raw)
In-Reply-To: <20221021185615.605233-2-terry.bowman@amd.com>

Terry Bowman wrote:
> ACPI includes a CXL _OSC support method to communicate the available
> CXL support to FW. The CXL support _OSC includes a field to indicate
> CXL1.1 RCH RCD support. The OS sets this bit to 1 if it supports access
> to RCD and RCH Port registers.[1] FW can potentially change it's operation
> depending on the _OSC support setting reported by the OS.
> 
> The ACPI driver does not currently set the ACPI _OSC support to indicate
> CXL1.1 RCD RCH support. Change the capability reported to include CXL1.1.
> 
> [1] CXL3.0 Table 9-26 'Interpretation of CXL _OSC Support Field'
> 
> Signed-off-by: Terry Bowman <terry.bowman@amd.com>
> ---
>  drivers/acpi/pci_root.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/acpi/pci_root.c b/drivers/acpi/pci_root.c
> index c8385ef54c37..094a59b216ae 100644
> --- a/drivers/acpi/pci_root.c
> +++ b/drivers/acpi/pci_root.c

Be sure to copy linux-acpi@vger.kernel.org on patches that touch
drivers/acpi/

> @@ -492,6 +492,7 @@ static u32 calculate_cxl_support(void)
>  	u32 support;
>  
>  	support = OSC_CXL_2_0_PORT_DEV_REG_ACCESS_SUPPORT;
> +	support |= OSC_CXL_1_1_PORT_REG_ACCESS_SUPPORT;
>  	if (pci_aer_available())
>  		support |= OSC_CXL_PROTOCOL_ERR_REPORTING_SUPPORT;
>  	if (IS_ENABLED(CONFIG_HOTPLUG_PCI_PCIE))

This looks good to me though.

  reply	other threads:[~2022-10-21 22:39 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-10-21 18:56 [PATCH 0/5] cxl: Log downport PCIe AER and CXL RAS error information Terry Bowman
2022-10-21 18:56 ` [PATCH 1/5] cxl/acpi: Set ACPI's CXL _OSC to indicate CXL1.1 support Terry Bowman
2022-10-21 22:39   ` Dan Williams [this message]
2022-10-25 16:23     ` Terry Bowman
2022-10-21 18:56 ` [PATCH 2/5] cxl/pci: Discover and cache pointer to RCD dport's PCIe AER capability Terry Bowman
2022-10-22 21:45   ` Dan Williams
2022-10-25 16:42     ` Terry Bowman
2022-10-25 18:21       ` Dan Williams
2022-10-27 14:52   ` Bjorn Helgaas
2022-10-28 14:38     ` Terry Bowman
2022-10-21 18:56 ` [PATCH 3/5] cxl/pci: Discover and cache pointer to RCD dport's CXL RAS registers Terry Bowman
2022-10-22 22:44   ` Dan Williams
2022-10-26 19:01     ` Terry Bowman
2022-10-27 20:32       ` Dan Williams
2022-10-31 16:17         ` Terry Bowman
2022-10-28 12:53   ` Ariel.Sibley
2022-10-28 14:46     ` Terry Bowman
2022-10-21 18:56 ` [PATCH 4/5] cxl/pci: Enable RCD dport AER reporting Terry Bowman
2022-10-21 18:56 ` [PATCH 5/5] cxl/pci: Log CXL device's PCIe AER and CXL RAS error information Terry Bowman
2022-10-24 15:14   ` Jonathan Cameron
2022-10-27 21:30   ` Bjorn Helgaas
2022-10-21 19:02 ` [PATCH 0/5] cxl: Log downport " Terry Bowman
2022-10-28 12:30 ` Ariel.Sibley
2022-10-28 14:29   ` Terry Bowman
2022-10-28 16:37     ` Ariel.Sibley

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