From: Ira Weiny <ira.weiny@intel.com>
To: <shiju.jose@huawei.com>, <dave.jiang@intel.com>,
<dan.j.williams@intel.com>, <jonathan.cameron@huawei.com>,
<alison.schofield@intel.com>, <nifan.cxl@gmail.com>,
<vishal.l.verma@intel.com>, <ira.weiny@intel.com>,
<dave@stgolabs.net>, <linux-cxl@vger.kernel.org>
Cc: <linux-kernel@vger.kernel.org>, <linuxarm@huawei.com>,
<tanxiaofei@huawei.com>, <prime.zeng@hisilicon.com>,
<shiju.jose@huawei.com>
Subject: Re: [PATCH v5 3/6] cxl/events: Update General Media Event Record to CXL spec rev 3.1
Date: Fri, 10 Jan 2025 11:54:43 -0600 [thread overview]
Message-ID: <67815ee3cb511_177894294a4@iweiny-mobl.notmuch> (raw)
In-Reply-To: <20250110115556.1654-4-shiju.jose@huawei.com>
shiju.jose@ wrote:
> From: Shiju Jose <shiju.jose@huawei.com>
>
> CXL spec rev 3.1 section 8.2.9.2.1.1 Table 8-45, General Media Event
> Record has updated with following new fields and new types for Memory
> Event Type and Transaction Type fields.
> 1. Advanced Programmable Corrected Memory Error Threshold Event Flags
> 2. Corrected Memory Error Count at Event
> 3. Memory Event Sub-Type
>
> The format of component identifier has changed (CXL spec 3.1 section
> 8.2.9.2.1 Table 8-44).
>
> Update the general media event record and general media trace event for
> the above spec changes. The new fields are inserted in logical places.
>
> Example trace log of cxl_general_media trace event,
>
> cxl_general_media: memdev=mem0 host=0000:0f:00.0 serial=3 log=Fatal : \
> time=156831237413 uuid=fbcd0a77-c260-417f-85a9-088b1621eba6 len=128 \
> flags='0x1' handle=1 related_handle=0 maint_op_class=2 \
> maint_op_sub_class=4 : dpa=30d40 dpa_flags='' \
> descriptor='UNCORRECTABLE_EVENT|THRESHOLD_EVENT|POISON_LIST_OVERFLOW' \
> type='TE State Violation' sub_type='Media Link Command Training Error' \
> transaction_type='Host Inject Poison' channel=3 rank=33 device=5 \
> validity_flags='CHANNEL|RANK|DEVICE|COMPONENT|COMPONENT PLDM FORMAT' \
> comp_id=03 74 c5 08 9a 1a 0b fc d2 7e 2f 31 9b 3c 81 4d \
> comp_id_pldm_valid_flags='PLDM Entity ID | Resource ID' \
> pldm_entity_id=74 c5 08 9a 1a 0b pldm_resource_id=fc d2 7e 2f \
> hpa=ffffffffffffffff region= \
> region_uuid=00000000-0000-0000-0000-000000000000 \
> cme_threshold_ev_flags='Corrected Memory Errors in Multiple Media \
> Components|Exceeded Programmable Threshold' cme_count=120
>
> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> Reviewed-by: Davidlohr Bueso <dave@stgolabs.net>
Reviewed-by: Ira Weiny <ira.weiny@intel.com>
[snip]
next prev parent reply other threads:[~2025-01-10 17:55 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-01-10 11:55 [PATCH v5 0/6] Update Event Records to CXL spec rev 3.1 shiju.jose
2025-01-10 11:55 ` [PATCH v5 1/6] cxl/events: Update Common Event Record " shiju.jose
2025-01-10 17:35 ` Ira Weiny
2025-01-10 11:55 ` [PATCH v5 2/6] cxl/events: Add Component Identifier formatting for " shiju.jose
2025-01-10 17:43 ` Ira Weiny
2025-01-10 11:55 ` [PATCH v5 3/6] cxl/events: Update General Media Event Record to " shiju.jose
2025-01-10 17:54 ` Ira Weiny [this message]
2025-01-10 18:30 ` Ira Weiny
2025-01-10 11:55 ` [PATCH v5 4/6] cxl/events: Update DRAM " shiju.jose
2025-01-10 18:27 ` Ira Weiny
2025-01-11 9:16 ` Shiju Jose
2025-01-10 11:55 ` [PATCH v5 5/6] cxl/events: Update Memory Module " shiju.jose
2025-01-10 18:46 ` Ira Weiny
2025-01-10 11:55 ` [PATCH v5 6/6] cxl/test: Update test code for event records " shiju.jose
2025-01-10 18:48 ` Ira Weiny
2025-01-10 16:06 ` [PATCH v5 0/6] Update Event Records " Jonathan Cameron
2025-01-10 16:46 ` Shiju Jose
2025-01-10 20:18 ` Dave Jiang
2025-01-11 9:22 ` Shiju Jose
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