From: Dan Williams <dan.j.williams@intel.com>
To: Ben Cheatham <benjamin.cheatham@amd.com>,
<alejandro.lucero-palau@amd.com>
Cc: Alejandro Lucero <alucerop@amd.com>, <linux-cxl@vger.kernel.org>,
<dan.j.williams@intel.com>
Subject: Re: [RFC 0/2] type2 cxl initialization
Date: Mon, 3 Mar 2025 12:49:30 -0800 [thread overview]
Message-ID: <67c615da5dd98_1a772947d@dwillia2-xfh.jf.intel.com.notmuch> (raw)
In-Reply-To: <289fc275-43b6-424c-8c0c-28c5d527ac35@amd.com>
Ben Cheatham wrote:
> On 2/20/25 2:00 PM, alejandro.lucero-palau@amd.com wrote:
> > From: Alejandro Lucero <alucerop@amd.com>
> >
> > Avoiding to send the full type2 support patchset until there is an
> > agreement about how to do the cxl initialization from accel drivers.
> >
> > Using the idea from fwctl for embedding cxl_dev_state in a private
> > accel driver struct and a macro helping for the allocation and
> > initialization of such struct.
> >
> > The main problem is the amount of internal cxl structs which need to be
> > public for accel drivers which we tried to avoid since v1 of the type2
> > patchset history.
>
> I have a suggestion or two in the next patch, but in my opinion the only
> potentially problematic exports are the cxl register structs. I'm assuming
> allowing accelerator drivers access to those may cause stale values in the
> CXL driver, but I haven't looked. The only suggestion I have there is to
> use pointers to the struct instead, but I imagine achieving could be a
> non-trivial amount of effort.
Hmm, say more about why you think those are a problem. Those are
"write-once at init" things, why would an accelerator driver have any
reason to play with those post init?
> The only other member that may be a problem is the DPA partition info,
> but I don't know enough about that to comment.
I think it is sufficient to mark the bulk of 'struct cxl_dev_state' as
private and then move things into the public space as needed, something
like:
struct cxl_dev_state {
/* public */
struct device *dev;
struct cxl_memdev *cxlmd;
/* private */
struct cxl_register_map reg_map;
struct cxl_regs regs;
int cxl_dvsec;
bool rcd;
bool media_ready;
struct resource dpa_res;
struct cxl_dpa_partition part[CXL_NR_PARTITIONS_MAX];
unsigned int nr_partitions;
u64 serial;
enum cxl_devtype type;
struct cxl_mailbox cxl_mbox;
};
...but otherwise let accelerator drivers see the full definition of that
struct for constainer_of() operations.
next prev parent reply other threads:[~2025-03-03 20:49 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-20 20:00 [RFC 0/2] type2 cxl initialization alejandro.lucero-palau
2025-02-20 20:00 ` [RFC type cxl initialization 1/2] cxl: add type2 device basic support alejandro.lucero-palau
2025-03-03 20:15 ` Dan Williams
2025-03-04 14:21 ` Alejandro Lucero Palau
2025-03-03 20:39 ` Ben Cheatham
2025-03-03 20:51 ` Dan Williams
2025-03-03 21:26 ` Ben Cheatham
2025-02-20 20:00 ` [RFC type cxl initialization 2/2] sfc: add cxl support alejandro.lucero-palau
2025-03-03 20:26 ` Dan Williams
2025-03-03 20:38 ` [RFC 0/2] type2 cxl initialization Ben Cheatham
2025-03-03 20:49 ` Dan Williams [this message]
2025-03-03 21:26 ` Ben Cheatham
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