From: Alejandro Lucero Palau <alucerop@amd.com>
To: "Cheatham, Benjamin" <bcheatha@amd.com>, alejandro.lucero-palau@amd.com
Cc: Martin Habets <habetsm.xilinx@gmail.com>,
Zhi Wang <zhi@nvidia.com>, Edward Cree <ecree.xilinx@gmail.com>,
Jonathan Cameron <Jonathan.Cameron@huawei.com>,
linux-cxl@vger.kernel.org, netdev@vger.kernel.org,
dan.j.williams@intel.com, edward.cree@amd.com,
davem@davemloft.net, kuba@kernel.org, pabeni@redhat.com,
edumazet@google.com, dave.jiang@intel.com,
Ben Cheatham <Benjamin.Cheatham@amd.com>
Subject: Re: [PATCH v15 06/22] sfc: make regs setup with checking and set media ready
Date: Wed, 14 May 2025 08:50:18 +0100 [thread overview]
Message-ID: <7c01b39c-72b4-4530-8ec2-f6e68e12c4a3@amd.com> (raw)
In-Reply-To: <7a951b14-c1df-488e-b63b-cdcb4a854b5c@amd.com>
On 5/13/25 19:27, Cheatham, Benjamin wrote:
> On 5/12/2025 11:10 AM, alejandro.lucero-palau@amd.com wrote:
>> From: Alejandro Lucero <alucerop@amd.com>
>>
>> Use cxl code for registers discovery and mapping.
>>
>> Validate capabilities found based on those registers against expected
>> capabilities.
>>
>> Set media ready explicitly as there is no means for doing so without
>> a mailbox and without the related cxl register, not mandatory for type2.
>>
>> Signed-off-by: Alejandro Lucero <alucerop@amd.com>
>> Reviewed-by: Martin Habets <habetsm.xilinx@gmail.com>
>> Reviewed-by: Zhi Wang <zhi@nvidia.com>
>> Acked-by: Edward Cree <ecree.xilinx@gmail.com>
>> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
>> ---
>> drivers/net/ethernet/sfc/efx_cxl.c | 27 +++++++++++++++++++++++++++
>> 1 file changed, 27 insertions(+)
>>
>> diff --git a/drivers/net/ethernet/sfc/efx_cxl.c b/drivers/net/ethernet/sfc/efx_cxl.c
>> index 753d5b7d49b6..79427a85a1b7 100644
>> --- a/drivers/net/ethernet/sfc/efx_cxl.c
>> +++ b/drivers/net/ethernet/sfc/efx_cxl.c
>> @@ -19,10 +19,13 @@
>>
>> int efx_cxl_init(struct efx_probe_data *probe_data)
>> {
>> + DECLARE_BITMAP(expected, CXL_MAX_CAPS) = {};
>> + DECLARE_BITMAP(found, CXL_MAX_CAPS) = {};
>> struct efx_nic *efx = &probe_data->efx;
>> struct pci_dev *pci_dev = efx->pci_dev;
>> struct efx_cxl *cxl;
>> u16 dvsec;
>> + int rc;
>>
>> probe_data->cxl_pio_initialised = false;
>>
>> @@ -43,6 +46,30 @@ int efx_cxl_init(struct efx_probe_data *probe_data)
>> if (!cxl)
>> return -ENOMEM;
>>
>> + set_bit(CXL_DEV_CAP_HDM, expected);
>> + set_bit(CXL_DEV_CAP_HDM, expected);
> You have duplicate lines here. I think I pointed this out a couple of
> revisions ago, but it probably got missed.
>
> Thanks,
> Ben
>
Hi Ben,
Yes, apologies. I missed this one.
I'll definitely fix it in v16 later today.
Thank you!
next prev parent reply other threads:[~2025-05-14 7:50 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-12 16:10 [PATCH v15 00/22] Type2 device basic support alejandro.lucero-palau
2025-05-12 16:10 ` [PATCH v15 01/22] cxl: Add type2 " alejandro.lucero-palau
2025-05-12 16:10 ` [PATCH v15 02/22] sfc: add cxl support alejandro.lucero-palau
2025-05-12 16:10 ` [PATCH v15 03/22] cxl: Move pci generic code alejandro.lucero-palau
2025-05-12 16:10 ` [PATCH v15 04/22] cxl: Move register/capability check to driver alejandro.lucero-palau
2025-05-12 16:10 ` [PATCH v15 05/22] cxl: Add function for type2 cxl regs setup alejandro.lucero-palau
2025-05-12 16:10 ` [PATCH v15 06/22] sfc: make regs setup with checking and set media ready alejandro.lucero-palau
2025-05-13 18:27 ` Cheatham, Benjamin
2025-05-14 7:50 ` Alejandro Lucero Palau [this message]
2025-05-12 16:10 ` [PATCH v15 07/22] cxl: Support dpa initialization without a mailbox alejandro.lucero-palau
2025-05-12 16:10 ` [PATCH v15 08/22] sfc: initialize dpa alejandro.lucero-palau
2025-05-12 16:10 ` [PATCH v15 09/22] cxl: Prepare memdev creation for type2 alejandro.lucero-palau
2025-05-12 16:10 ` [PATCH v15 10/22] sfc: create type2 cxl memdev alejandro.lucero-palau
2025-05-12 16:10 ` [PATCH v15 11/22] cxl: Define a driver interface for HPA free space enumeration alejandro.lucero-palau
2025-05-12 16:10 ` [PATCH v15 12/22] sfc: obtain root decoder with enough HPA free space alejandro.lucero-palau
2025-05-12 16:10 ` [PATCH v15 13/22] cxl: Define a driver interface for DPA allocation alejandro.lucero-palau
2025-05-12 16:10 ` [PATCH v15 14/22] sfc: get endpoint decoder alejandro.lucero-palau
2025-05-12 16:10 ` [PATCH v15 15/22] cxl: Make region type based on endpoint type alejandro.lucero-palau
2025-05-12 16:10 ` [PATCH v15 16/22] cxl/region: Factor out interleave ways setup alejandro.lucero-palau
2025-05-12 16:10 ` [PATCH v15 17/22] cxl/region: Factor out interleave granularity setup alejandro.lucero-palau
2025-05-12 16:10 ` [PATCH v15 18/22] cxl: Allow region creation by type2 drivers alejandro.lucero-palau
2025-05-12 16:10 ` [PATCH v15 19/22] cxl: Add region flag for precluding a device memory to be used for dax alejandro.lucero-palau
2025-05-12 16:10 ` [PATCH v15 20/22] sfc: create cxl region alejandro.lucero-palau
2025-05-12 16:10 ` [PATCH v15 21/22] cxl: Add function for obtaining region range alejandro.lucero-palau
2025-05-12 16:10 ` [PATCH v15 22/22] sfc: support pio mapping based on cxl alejandro.lucero-palau
2025-05-12 22:36 ` [PATCH v15 00/22] Type2 device basic support Dave Jiang
2025-05-13 8:12 ` Alejandro Lucero Palau
2025-05-13 15:13 ` Dave Jiang
2025-05-13 15:24 ` Alejandro Lucero Palau
2025-05-13 16:04 ` Dave Jiang
2025-05-13 16:21 ` Alejandro Lucero Palau
2025-05-13 16:38 ` Dave Jiang
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