From: PJ Waskiewicz <ppwaskie@kernel.org>
To: Dave Jiang <dave.jiang@intel.com>,
linux-cxl@vger.kernel.org, linux-pci@vger.kernel.org
Cc: dan.j.williams@intel.com, ira.weiny@intel.com,
vishal.l.verma@intel.com, alison.schofield@intel.com,
Jonathan.Cameron@huawei.com, dave@stgolabs.net,
bhelgaas@google.com, lukas@wunner.de,
Bjorn Helgaas <helgaas@kernel.org>,
Kuppuswamy Sathyanarayanan
<sathyanarayanan.kuppuswamy@linux.intel.com>
Subject: Re: [PATCH v5 1/4] PCI/cxl: Move PCI CXL vendor Id to a common location from CXL subsystem
Date: Wed, 01 May 2024 08:37:38 -0700 [thread overview]
Message-ID: <91fe797284f433a76bdc1f804a6d86e0077a905f.camel@kernel.org> (raw)
In-Reply-To: <20240429223610.1341811-2-dave.jiang@intel.com>
On Mon, 2024-04-29 at 15:35 -0700, Dave Jiang wrote:
> Move PCI_DVSEC_VENDOR_ID_CXL in CXL private code to PCI_VENDOR_ID_CXL
> in
> pci_ids.h in order to be utilized in PCI subsystem.
>
> When uplevelling PCI_DVSEC_VENDOR_ID_CXL to a common locatoin Bjorn
> suggested making it a proper PCI_VENDOR_ID_* define in
> include/linux/pci_ids.h. While it is not in the PCI IDs database it
> is a
> reserved value and Linux treats it as a 'vendor id' for all intents
> and
> purposes [1].
Would you consider a patch, after this series merges, to upstream
pciutils to sync up lspci's name of this value as well? It would be
less confusing to anyone looking at both codebases and trying to line
up #define's.
-PJ
next prev parent reply other threads:[~2024-05-01 15:37 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-29 22:35 [PATCH v5 0/4] PCI: Add Secondary Bus Reset (SBR) support for CXL Dave Jiang
2024-04-29 22:35 ` [PATCH v5 1/4] PCI/cxl: Move PCI CXL vendor Id to a common location from CXL subsystem Dave Jiang
2024-05-01 15:37 ` PJ Waskiewicz [this message]
2024-05-01 16:04 ` Dave Jiang
2024-05-01 16:09 ` Dan Williams
2024-04-29 22:35 ` [PATCH v5 2/4] PCI: Add check for CXL Secondary Bus Reset Dave Jiang
2024-05-01 19:47 ` Dan Williams
2024-04-29 22:35 ` [PATCH v5 3/4] PCI: Create new reset method to force SBR for CXL Dave Jiang
2024-05-02 2:51 ` Dan Williams
2024-04-29 22:35 ` [PATCH v5 4/4] cxl: Add post reset warning if reset results in loss of previously committed HDM decoders Dave Jiang
2024-05-02 2:55 ` Dan Williams
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