messages from 2023-06-22 21:39:49 to 2023-07-13 21:50:59 UTC [more...]
[PATCH v9] cxl: add RAS status unmasking for CXL
2023-07-13 21:50 UTC (4+ messages)
[PATCH -ndctl v2 0/2] cxl: Support memdev sanitation
2023-07-13 19:54 UTC (3+ messages)
` [PATCH 1/2] cxl/memdev: Introduce wait-sanitize functionality
` [PATCH 2/2] cxl/memdev: Introduce sanitize-memdev functionality
[PATCH v2] cxl: Update MAINTAINERS
2023-07-13 20:38 UTC (5+ messages)
[PATCH 0/3] mm: use memmap_on_memory semantics for dax/kmem
2023-07-13 19:12 UTC (16+ messages)
` [PATCH 1/3] mm/memory_hotplug: Allow an override for the memmap_on_memory param
` [PATCH 3/3] dax/kmem: Always enroll hotplugged memory for memmap_on_memory
[PATCH 0/5] cxl/dcd: Add support for Dynamic Capacity Devices (DCD)
2023-07-13 12:55 UTC (21+ messages)
` [PATCH 1/5] cxl/mem : Read Dynamic capacity configuration from the device
` [PATCH 2/5] cxl/region: Add dynamic capacity cxl region support
` [PATCH 4/5] cxl/mem: Add support to handle DCD add and release capacity events
[PATCH v2] cxl/acpi: Release device after dev_err()
2023-07-13 4:38 UTC (7+ messages)
[PATCH] cxl/mem: Fix a double shift bug
2023-07-12 19:34 UTC (4+ messages)
[PATCH] cxl: Fix double shift of CXL_FW_CANCEL
2023-07-12 18:02 UTC (4+ messages)
[PATCH] cxl/pci: Remove unnecessary aer.h include
2023-07-12 16:02 UTC (3+ messages)
[PATCH] cxl: Update MAINTAINERS
2023-07-12 15:07 UTC (4+ messages)
[Question] How to set up DVSEC CXL Range Registers for DCD devices
2023-07-12 8:48 UTC (5+ messages)
[ndctl PATCH v4 0/4] cxl/monitor and ndctl/monitor fixes
2023-07-11 17:58 UTC (9+ messages)
` [ndctl PATCH v4 1/4] cxl/monitor: Enable default_log and refactor sanity check
` [ndctl PATCH v4 2/4] cxl/monitor: replace monitor.log_file with monitor.ctx.log_file
` [ndctl PATCH v4 3/4] ndctl: use strcmp for reserved word in monitor commands
` [ndctl PATCH v4 4/4] Documentation/cxl/cxl-monitor.txt: Fix inaccurate description
[ndctl PATCH 0/2] add support for Set Alert Configuration mailbox command
2023-07-11 7:10 UTC (3+ messages)
` [ndctl PATCH 1/2] libcxl: "
` [ndctl PATCH 2/2] cxl: add 'set-alert-config' command to cxl tool
[PATCH v4 0/2] CXL: Apply SRAT defined PXM to entire CFMWS window
2023-07-10 20:02 UTC (3+ messages)
` [PATCH v4 1/2] x86/numa: Introduce numa_fill_memblks()
` [PATCH v4 2/2] ACPI: NUMA: Apply SRAT proximity domain to entire CFMWS window
[ndctl PATCH v3 0/6] cxl/monitor and ndctl/monitor fixes
2023-07-10 16:59 UTC (22+ messages)
` [ndctl PATCH v3 1/6] cxl/monitor: Enable default_log and refactor sanity check
` [ndctl PATCH v3 2/6] cxl/monitor: replace monitor.log_file with monitor.ctx.log_file
` [ndctl PATCH v3 3/6] cxl/monitor: use strcmp to compare the reserved word
` [ndctl PATCH v3 4/6] cxl/monitor: always log started message
` [ndctl PATCH v3 6/6] ndctl/monitor: use strcmp to compare the reserved word
[PATCH] cxl/acpi: Release device after dev_err
2023-07-10 15:55 UTC (8+ messages)
[NDCTL PATCH] cxl/region: Always use the correct target position
2023-07-09 11:50 UTC (2+ messages)
[PATCH] memory tier: rename destroy_memory_type() to put_memory_type()
2023-07-06 13:11 UTC (3+ messages)
[PATCH] cxl: fix CONFIG_FW_LOADER dependency
2023-07-06 10:50 UTC (3+ messages)
[PATCH v8 00/14] cxl/pci: Add support for RCH RAS error handling
2023-07-04 0:39 UTC (18+ messages)
` [PATCH v8 01/14] cxl/port: Pre-initialize component register mappings
` [PATCH v8 02/14] cxl/pci: Store the endpoint's Component Register mappings in struct cxl_dev_state
` [PATCH v8 03/14] cxl/hdm: Use stored Component Register mappings to map HDM decoder capability
` [PATCH v8 04/14] cxl/pci: Remove Component Register base address from struct cxl_dev_state
` [PATCH v8 05/14] cxl/port: Remove Component Register base address from struct cxl_port
` [PATCH v8 06/14] cxl/pci: Add RCH downstream port AER register discovery
` [PATCH v8 07/14] PCI/AER: Refactor cper_print_aer() for use by CXL driver module
` [PATCH v8 08/14] cxl/pci: Update CXL error logging to use RAS register address
` [PATCH v8 09/14] cxl/pci: Map RCH downstream AER registers for logging protocol errors
` [PATCH v8 10/14] cxl/pci: Add RCH downstream port error logging
` [PATCH v8 11/14] cxl/pci: Disable root port interrupts in RCH mode
` [PATCH v8 12/14] PCI/AER: Forward RCH downstream port-detected errors to the CXL.mem dev handler
` [PATCH v8 13/14] PCI/AER: Unmask RCEC internal errors to enable RCH downstream port error handling
` [PATCH v8 14/14] cxl/core/regs: Rename phys_addr in cxl_map_component_regs()
[PATCH v7 00/27] cxl/pci: Add support for RCH RAS error handling
2023-07-03 3:55 UTC (28+ messages)
` [PATCH v7 01/27] cxl/acpi: Probe RCRB later during RCH downstream port creation
` [PATCH v7 14/27] cxl/port: Store the port's Component Register mappings in struct cxl_port
` [PATCH v7 16/27] cxl/pci: Store the endpoint's Component Register mappings in struct cxl_dev_state
` [PATCH v7 20/27] PCI/AER: Refactor cper_print_aer() for use by CXL driver module
` [PATCH v7 21/27] cxl/pci: Update CXL error logging to use RAS register address
` [PATCH v7 22/27] cxl/pci: Map RCH downstream AER registers for logging protocol errors
` [PATCH v7 23/27] cxl/pci: Add RCH downstream port error logging
` [PATCH v7 24/27] cxl/pci: Disable root port interrupts in RCH mode
` [PATCH v7 25/27] PCI/AER: Forward RCH downstream port-detected errors to the CXL.mem dev handler
` [PATCH v7 26/27] PCI/AER: Unmask RCEC internal errors to enable RCH downstream port error handling
` [PATCH v7 27/27] cxl/core/regs: Rename phys_addr in cxl_map_component_regs()
[Qemu RFC 0/7] Early enabling of DCD emulation in Qemu
2023-07-03 1:33 UTC (14+ messages)
` [RFC 2/7] hw/cxl/cxl-mailbox-utils: Add dynamic capacity region representative and mailbox command support
` [RFC 7/7] hw/mem/cxl_type3: add read/write support to dynamic capacity
` [RFC 5/7] hw/cxl/cxl-mailbox-utils: Add mailbox commands to support add/release dynamic capacity response
[GIT PULL] Compute Express Link (CXL) for 6.5
2023-07-01 16:12 UTC (2+ messages)
[cxl:next] BUILD SUCCESS fe77cc2e5a6a7c85f5c6ef8a39d7694ffc7f41c9
2023-07-01 11:36 UTC
[PATCH v3] dax/kmem: Pass valid argument to memory_group_register_static
2023-06-30 3:41 UTC (2+ messages)
[PATCH -next] cxl: Fix one kernel-doc comment
2023-06-29 23:22 UTC (2+ messages)
[cxl:next] BUILD SUCCESS 71baec7b8500c92f9723f39d06a7ae465483da1f
2023-06-28 13:38 UTC
[PATCH v6 0/7] cxl: Support device sanitation
2023-06-27 23:01 UTC (12+ messages)
` [PATCH 3/7] cxl/mbox: Add sanitation handling machinery
` [PATCH 4/7] cxl/mem: Wire up Sanitation support
` [PATCH] cxl/pci: Use correct flag for sanitize polling
[cxl:pending] BUILD SUCCESS 0c0df63177e37ae826d803280eb2c5b6b6a7a9a4
2023-06-27 1:20 UTC
[PATCH v3 0/2] CXL: Apply SRAT defined PXM to entire CFMWS window
2023-06-27 0:49 UTC (5+ messages)
` [PATCH v3 1/2] x86/numa: Introduce numa_fill_memblks()
` [PATCH v3 2/2] ACPI: NUMA: Apply SRAT proximity domain to entire CFMWS window
[PATCH v8 0/5] perf: CXL 3.0 Performance Monitoring Unit support
2023-06-26 0:46 UTC (3+ messages)
` [PATCH v8 3/5] cxl/pci: Find and register CXL PMU devices
[PATCH 0/3] cxl/region: Cache management and region decode reset fixes
2023-06-25 20:42 UTC (4+ messages)
` [PATCH 3/3] cxl/region: Fix state transitions after reset failure
[PATCH 0/2] cxl/region: Improve Soft Reserved resource handling
2023-06-24 1:24 UTC (3+ messages)
` [PATCH 1/2] cxl/region: Try to add a region resource to a soft reserved parent
` [PATCH 2/2] cxl/region: Remove a soft reserved resource at region teardown
How to find the base address of CXL 1.1 Downstream Port RCRB for specific device
2023-06-23 21:46 UTC
[PATCH v6 00/27] cxl/pci: Add support for RCH RAS error handling
2023-06-23 13:28 UTC (43+ messages)
` [PATCH v6 02/27] cxl/acpi: Probe RCRB later during RCH downstream port creation
` [PATCH v6 03/27] cxl: Updates for CXL Test to work with RCH
` [PATCH v6 04/27] cxl/rch: Prepare for caching the MMIO mapped PCIe AER capability
` [PATCH v6 05/27] cxl: Rename member @dport of struct cxl_dport to @dport_dev
` [PATCH v6 06/27] cxl: Rename 'uport' to 'uport_dev'
` [PATCH v6 07/27] cxl/core/regs: Add @dev to cxl_register_map
` [PATCH v6 08/27] cxl/pci: Refactor component register discovery for reuse
` [PATCH v6 09/27] cxl/acpi: Move add_host_bridge_uport() after cxl_get_chbs()
` [PATCH v6 10/27] cxl/acpi: Directly bind the CEDT detected CHBCR to the Host Bridge's port
` [PATCH v6 11/27] cxl/port: Remove Component Register base address from struct cxl_dport
` [PATCH v6 12/27] cxl/regs: Remove early capability checks in Component Register setup
` [PATCH v6 13/27] cxl/mem: Prepare for early RCH dport component register setup
` [PATCH v6 14/27] cxl/pci: Early setup RCH dport component registers from RCRB
` [PATCH v6 15/27] cxl/port: Store the port's Component Register mappings in struct cxl_port
` [PATCH v6 16/27] cxl/port: Store the downstream port's Component Register mappings in struct cxl_dport
` [PATCH v6 17/27] cxl/pci: Store the endpoint's Component Register mappings in struct cxl_dev_state
` [PATCH v6 18/27] cxl/hdm: Use stored Component Register mappings to map HDM decoder capability
` [PATCH v6 19/27] cxl/port: Remove Component Register base address from struct cxl_port
` [PATCH v6 20/27] cxl/pci: Add RCH downstream port AER register discovery
` [PATCH v6 25/27] cxl/pci: Disable root port interrupts in RCH mode
[PATCH v8 0/4] hw/cxl: Poison get, inject, clear
2023-06-23 12:13 UTC (4+ messages)
[PATCH v4 0/6] acpi: numa: add target support for generic port to HMAT parsing
2023-06-22 21:40 UTC (5+ messages)
` [PATCH v4 3/6] acpi: numa: Add genport target allocation to the "
` [PATCH v4 4/6] acpi: Break out nesting for hmat_parse_locality()
` [PATCH v4 5/6] acpi: numa: Add setting of generic port system locality attributes
` [PATCH v4 6/6] acpi: numa: Add helper function to retrieve the performance attributes
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