* [PATCH] cxl: Fix double shift of CXL_FW_CANCEL
@ 2023-07-12 16:42 Davidlohr Bueso
2023-07-12 17:39 ` Verma, Vishal L
2023-07-12 17:59 ` Dave Jiang
0 siblings, 2 replies; 4+ messages in thread
From: Davidlohr Bueso @ 2023-07-12 16:42 UTC (permalink / raw)
To: dan.j.williams
Cc: vishal.l.verma, jonathan.cameron, fan.ni, dave.jiang,
a.manzanares, dave, linux-cxl
Directly use the bit number for bitops, which already has a shift
built in. This bug is benign as its done consistently and it doesn't
clash with any other flags.
Fixes: 9521875bbe00 ("cxl: add a firmware update mechanism using the sysfs firmware loader")
Signed-off-by: Davidlohr Bueso <dave@stgolabs.net>
---
drivers/cxl/cxlmem.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h
index 79e99c873ca2..499113328586 100644
--- a/drivers/cxl/cxlmem.h
+++ b/drivers/cxl/cxlmem.h
@@ -323,7 +323,7 @@ struct cxl_mbox_activate_fw {
/* FW state bits */
#define CXL_FW_STATE_BITS 32
-#define CXL_FW_CANCEL BIT(0)
+#define CXL_FW_CANCEL 0
/**
* struct cxl_fw_state - Firmware upload / activation state
--
2.41.0
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH] cxl: Fix double shift of CXL_FW_CANCEL
2023-07-12 16:42 [PATCH] cxl: Fix double shift of CXL_FW_CANCEL Davidlohr Bueso
@ 2023-07-12 17:39 ` Verma, Vishal L
2023-07-12 18:02 ` Davidlohr Bueso
2023-07-12 17:59 ` Dave Jiang
1 sibling, 1 reply; 4+ messages in thread
From: Verma, Vishal L @ 2023-07-12 17:39 UTC (permalink / raw)
To: Williams, Dan J, dave@stgolabs.net
Cc: Jiang, Dave, jonathan.cameron@huawei.com, fan.ni@samsung.com,
a.manzanares@samsung.com, linux-cxl@vger.kernel.org
On Wed, 2023-07-12 at 09:42 -0700, Davidlohr Bueso wrote:
> Directly use the bit number for bitops, which already has a shift
> built in. This bug is benign as its done consistently and it doesn't
> clash with any other flags.
Ah good catch!
>
> Fixes: 9521875bbe00 ("cxl: add a firmware update mechanism using the sysfs firmware loader")
> Signed-off-by: Davidlohr Bueso <dave@stgolabs.net>
Reviewed-by: Vishal Verma <vishal.l.verma@intel.com>
> ---
> drivers/cxl/cxlmem.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h
> index 79e99c873ca2..499113328586 100644
> --- a/drivers/cxl/cxlmem.h
> +++ b/drivers/cxl/cxlmem.h
> @@ -323,7 +323,7 @@ struct cxl_mbox_activate_fw {
>
> /* FW state bits */
> #define CXL_FW_STATE_BITS 32
> -#define CXL_FW_CANCEL BIT(0)
> +#define CXL_FW_CANCEL 0
>
> /**
> * struct cxl_fw_state - Firmware upload / activation state
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] cxl: Fix double shift of CXL_FW_CANCEL
2023-07-12 16:42 [PATCH] cxl: Fix double shift of CXL_FW_CANCEL Davidlohr Bueso
2023-07-12 17:39 ` Verma, Vishal L
@ 2023-07-12 17:59 ` Dave Jiang
1 sibling, 0 replies; 4+ messages in thread
From: Dave Jiang @ 2023-07-12 17:59 UTC (permalink / raw)
To: Davidlohr Bueso, dan.j.williams
Cc: vishal.l.verma, jonathan.cameron, fan.ni, a.manzanares, linux-cxl
On 7/12/23 09:42, Davidlohr Bueso wrote:
> Directly use the bit number for bitops, which already has a shift
> built in. This bug is benign as its done consistently and it doesn't
> clash with any other flags.
>
> Fixes: 9521875bbe00 ("cxl: add a firmware update mechanism using the sysfs firmware loader")
> Signed-off-by: Davidlohr Bueso <dave@stgolabs.net>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
> ---
> drivers/cxl/cxlmem.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h
> index 79e99c873ca2..499113328586 100644
> --- a/drivers/cxl/cxlmem.h
> +++ b/drivers/cxl/cxlmem.h
> @@ -323,7 +323,7 @@ struct cxl_mbox_activate_fw {
>
> /* FW state bits */
> #define CXL_FW_STATE_BITS 32
> -#define CXL_FW_CANCEL BIT(0)
> +#define CXL_FW_CANCEL 0
>
> /**
> * struct cxl_fw_state - Firmware upload / activation state
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] cxl: Fix double shift of CXL_FW_CANCEL
2023-07-12 17:39 ` Verma, Vishal L
@ 2023-07-12 18:02 ` Davidlohr Bueso
0 siblings, 0 replies; 4+ messages in thread
From: Davidlohr Bueso @ 2023-07-12 18:02 UTC (permalink / raw)
To: Verma, Vishal L
Cc: Williams, Dan J, Jiang, Dave, jonathan.cameron@huawei.com,
fan.ni@samsung.com, a.manzanares@samsung.com,
linux-cxl@vger.kernel.org
On Wed, 12 Jul 2023, Verma, Vishal L wrote:
>On Wed, 2023-07-12 at 09:42 -0700, Davidlohr Bueso wrote:
>> Directly use the bit number for bitops, which already has a shift
>> built in. This bug is benign as its done consistently and it doesn't
>> clash with any other flags.
>
>Ah good catch!
Actually this is a duplicate. I just noticed, scrolling the list, that Dan
Carpenter has already sent a fix for this. His patch should be picked up.
Sorry for the noise.
Thanks,
Davidlohr
^ permalink raw reply [flat|nested] 4+ messages in thread
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2023-07-12 16:42 [PATCH] cxl: Fix double shift of CXL_FW_CANCEL Davidlohr Bueso
2023-07-12 17:39 ` Verma, Vishal L
2023-07-12 18:02 ` Davidlohr Bueso
2023-07-12 17:59 ` Dave Jiang
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