From: Dave Jiang <dave.jiang@intel.com>
To: Davidlohr Bueso <dave@stgolabs.net>, <dan.j.williams@intel.com>
Cc: <vishal.l.verma@intel.com>, <jonathan.cameron@huawei.com>,
<fan.ni@samsung.com>, <a.manzanares@samsung.com>,
<linux-cxl@vger.kernel.org>
Subject: Re: [PATCH] cxl: Fix double shift of CXL_FW_CANCEL
Date: Wed, 12 Jul 2023 10:59:36 -0700 [thread overview]
Message-ID: <ebe2ad81-09ca-9e88-6b78-dcbe4fbf4219@intel.com> (raw)
In-Reply-To: <20230712164224.31891-1-dave@stgolabs.net>
On 7/12/23 09:42, Davidlohr Bueso wrote:
> Directly use the bit number for bitops, which already has a shift
> built in. This bug is benign as its done consistently and it doesn't
> clash with any other flags.
>
> Fixes: 9521875bbe00 ("cxl: add a firmware update mechanism using the sysfs firmware loader")
> Signed-off-by: Davidlohr Bueso <dave@stgolabs.net>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
> ---
> drivers/cxl/cxlmem.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h
> index 79e99c873ca2..499113328586 100644
> --- a/drivers/cxl/cxlmem.h
> +++ b/drivers/cxl/cxlmem.h
> @@ -323,7 +323,7 @@ struct cxl_mbox_activate_fw {
>
> /* FW state bits */
> #define CXL_FW_STATE_BITS 32
> -#define CXL_FW_CANCEL BIT(0)
> +#define CXL_FW_CANCEL 0
>
> /**
> * struct cxl_fw_state - Firmware upload / activation state
prev parent reply other threads:[~2023-07-12 17:59 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-12 16:42 [PATCH] cxl: Fix double shift of CXL_FW_CANCEL Davidlohr Bueso
2023-07-12 17:39 ` Verma, Vishal L
2023-07-12 18:02 ` Davidlohr Bueso
2023-07-12 17:59 ` Dave Jiang [this message]
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