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From: Ira Weiny <ira.weiny@intel.com>
To: Dan Williams <dan.j.williams@intel.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>,
	Jonathan Cameron <Jonathan.Cameron@huawei.com>,
	Ben Widawsky <bwidawsk@kernel.org>,
	"Alison Schofield" <alison.schofield@intel.com>,
	Vishal Verma <vishal.l.verma@intel.com>,
	Dave Jiang <dave.jiang@intel.com>, <linux-kernel@vger.kernel.org>,
	<linux-cxl@vger.kernel.org>, <linux-pci@vger.kernel.org>
Subject: Re: [PATCH V11 4/8] cxl/pci: Create PCI DOE mailbox's for memory devices
Date: Tue, 21 Jun 2022 11:29:35 -0700	[thread overview]
Message-ID: <YrIOD9ttvAabfyNu@iweiny-desk3> (raw)
In-Reply-To: <62ad11db18883_844b129415@dwillia2-xfh.notmuch>

On Fri, Jun 17, 2022 at 04:44:27PM -0700, Dan Williams wrote:
> ira.weiny@ wrote:

[snip]

> > diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h
> > index 60d10ee1e7fc..4d2764b865ab 100644
> > --- a/drivers/cxl/cxlmem.h
> > +++ b/drivers/cxl/cxlmem.h
> > @@ -191,6 +191,8 @@ struct cxl_endpoint_dvsec_info {
> >   * @component_reg_phys: register base of component registers
> >   * @info: Cached DVSEC information about the device.
> >   * @serial: PCIe Device Serial Number
> > + * @doe_mbs: PCI DOE mailbox array
> > + * @num_mbs: Number of DOE mailboxes
> >   * @mbox_send: @dev specific transport for transmitting mailbox commands
> >   *
> >   * See section 8.2.9.5.2 Capacity Configuration and Label Storage for
> > @@ -224,6 +226,10 @@ struct cxl_dev_state {
> >  	resource_size_t component_reg_phys;
> >  	u64 serial;
> >  
> > +	bool doe_use_irq;
> 
> Don't pass temporary state through a long lived data structure. Just
> pass flag by reference between the functions that want to coordinate
> this.

Done.

[snip]

> > +
> > +static void cxl_alloc_irq_vectors(struct cxl_dev_state *cxlds)
> > +{
> > +	struct device *dev = cxlds->dev;
> > +	struct pci_dev *pdev = to_pci_dev(dev);
> > +	int max_irqs = 0;
> > +	int off = 0;
> > +	int rc;
> > +
> > +	/* Account for all the DOE vectors needed */
> > +	pci_doe_for_each_off(pdev, off) {
> > +		int irq = pci_doe_get_irq_num(pdev, off);
> > +
> > +		if (irq < 0)
> > +			continue;
> > +		max_irqs = max(max_irqs, irq + 1);
> 
> This seems to assume that different DOEs will get independent vectors.
> The driver needs to be prepared for DOE instances, Event notifications,
> and mailbox commands to share a single MSI vector in the worst case.
> Lets focus on polled mode DOE, or explicitly only support interrupt
> based operation when no vector sharing is detected.
> 

Ok I see now.  I was under the impression they had to be unique.

Do you think it is sufficient to check in this loop for duplicates and bail if
any are shared?

Ira


  reply	other threads:[~2022-06-21 18:29 UTC|newest]

Thread overview: 44+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-06-10 20:22 [PATCH V11 0/8] CXL: Read CDAT and DSMAS data ira.weiny
2022-06-10 20:22 ` [PATCH V11 1/8] PCI: Add vendor ID for the PCI SIG ira.weiny
2022-06-10 20:22 ` [PATCH V11 2/8] PCI: Replace magic constant for PCI Sig Vendor ID ira.weiny
2022-06-10 20:22 ` [PATCH V11 3/8] PCI: Create PCI library functions in support of DOE mailboxes ira.weiny
2022-06-14  3:53   ` Li, Ming
2022-06-15  4:18     ` Ira Weiny
2022-06-17 22:40   ` Bjorn Helgaas
2022-06-18 16:39     ` Bjorn Helgaas
2022-06-22 16:46       ` Ira Weiny
2022-06-20  9:24     ` Jonathan Cameron
2022-06-22 23:06       ` Ira Weiny
2022-06-22 16:38     ` Ira Weiny
2022-06-17 22:56   ` Dan Williams
2022-06-20 10:23     ` Jonathan Cameron
2022-06-22 22:57       ` Ira Weiny
2022-06-23 18:03         ` Dan Williams
2022-06-22 22:37     ` Ira Weiny
2022-06-22 22:45     ` Ira Weiny
2022-06-22 22:57       ` Dan Williams
2022-06-23  0:25         ` Ira Weiny
2022-06-23 10:24           ` Jonathan Cameron
2022-06-23 18:14             ` Dan Williams
2022-06-23 18:07           ` Dan Williams
2022-06-10 20:22 ` [PATCH V11 4/8] cxl/pci: Create PCI DOE mailbox's for memory devices ira.weiny
2022-06-17 20:40   ` [PATCH v11 " Davidlohr Bueso
2022-06-17 20:51     ` Davidlohr Bueso
2022-06-21 18:24     ` Ira Weiny
2022-06-17 23:44   ` [PATCH V11 " Dan Williams
2022-06-21 18:29     ` Ira Weiny [this message]
2022-06-22 23:18       ` Ira Weiny
2022-06-21 20:37   ` Bjorn Helgaas
2022-06-10 20:22 ` [PATCH V11 5/8] cxl/port: Read CDAT table ira.weiny
2022-06-18  0:43   ` Dan Williams
2022-06-21 19:10     ` Dan Williams
2022-06-21 19:34       ` Lukas Wunner
2022-06-21 19:41         ` Dan Williams
2022-06-21 20:38           ` Ira Weiny
2022-06-21 21:14     ` Ira Weiny
2022-06-21 21:48       ` Dan Williams
2022-06-28  3:24         ` Ira Weiny
2022-06-10 20:22 ` [PATCH V11 6/8] cxl/port: Introduce cxl_cdat_valid() ira.weiny
2022-06-10 20:22 ` [PATCH V11 7/8] cxl/port: Retry reading CDAT on failure ira.weiny
2022-06-28  3:32   ` Alison Schofield
2022-06-10 20:22 ` [PATCH V11 8/8] cxl/port: Parse out DSMAS data from CDAT table ira.weiny

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