From: Alison Schofield <alison.schofield@intel.com>
To: Ira Weiny <ira.weiny@intel.com>
Cc: Davidlohr Bueso <dave@stgolabs.net>,
Jonathan Cameron <jonathan.cameron@huawei.com>,
Dave Jiang <dave.jiang@intel.com>,
Vishal Verma <vishal.l.verma@intel.com>,
Dan Williams <dan.j.williams@intel.com>,
linux-cxl@vger.kernel.org
Subject: Re: [PATCH] cxl/test: Define a CFMWS capable of a 3 way HB interleave
Date: Wed, 26 Feb 2025 14:19:07 -0800 [thread overview]
Message-ID: <Z7-TWwA6q6fBoJIB@aschofie-mobl2.lan> (raw)
In-Reply-To: <67bf7a8a66180_5bbaf29425@iweiny-mobl.notmuch>
On Wed, Feb 26, 2025 at 02:33:14PM -0600, Ira Weiny wrote:
> alison.schofield@ wrote:
> > From: Alison Schofield <alison.schofield@intel.com>
> >
> > The CXL unit test cxl-xor-region.sh is skipping a 1+1+1 region
> > interleave test case because the window is not defined.
> >
> > Additionally, upcoming expansion of 3 way HB interleave test cases
> > (like 2+2+2) require the same window.
> >
> > Replace an unused CFMWS with a 3-way capable CFMWS in the set of
> > CFMWS's loaded when interleave_arithmetic=1.
> >
> > Signed-off-by: Alison Schofield <alison.schofield@intel.com>
> > ---
> > tools/testing/cxl/test/cxl.c | 8 ++++----
> > 1 file changed, 4 insertions(+), 4 deletions(-)
> >
> > diff --git a/tools/testing/cxl/test/cxl.c b/tools/testing/cxl/test/cxl.c
> > index 083a66a52731..e5cd874614d2 100644
> > --- a/tools/testing/cxl/test/cxl.c
> > +++ b/tools/testing/cxl/test/cxl.c
> > @@ -331,14 +331,14 @@ static struct {
> > .length = sizeof(mock_cedt.cfmws8),
> > },
> > .interleave_arithmetic = ACPI_CEDT_CFMWS_ARITHMETIC_XOR,
> > - .interleave_ways = 2,
> > - .granularity = 0,
> > + .interleave_ways = 8,
> > + .granularity = 1,
> > .restrictions = ACPI_CEDT_CFMWS_RESTRICT_TYPE3 |
> > ACPI_CEDT_CFMWS_RESTRICT_PMEM,
> > .qtg_id = FAKE_QTG_ID,
> > - .window_size = SZ_256M * 16UL,
> > + .window_size = SZ_512M * 6UL,
> > },
> > - .target = { 0, 1, 0, 1, },
> > + .target = { 0, 1, 2, },
>
> Minor nit:
Not a nit. Thanks, revving!
>
> Reviewed-by: Ira Weiny <ira.weiny@intel.com>
>
> Should this also include:
>
> diff --git a/tools/testing/cxl/test/cxl.c b/tools/testing/cxl/test/cxl.c
> index cc8948f49117..f0b5b7b8d1d0 100644
> --- a/tools/testing/cxl/test/cxl.c
> +++ b/tools/testing/cxl/test/cxl.c
> @@ -155,7 +155,7 @@ static struct {
> } cfmws7;
> struct {
> struct acpi_cedt_cfmws cfmws;
> - u32 target[4];
> + u32 target[3];
> } cfmws8;
> struct {
> struct acpi_cedt_cxims cxims;
prev parent reply other threads:[~2025-02-26 22:19 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-24 23:50 [PATCH] cxl/test: Define a CFMWS capable of a 3 way HB interleave alison.schofield
2025-02-25 0:27 ` Dave Jiang
2025-02-26 7:22 ` Zhijian Li (Fujitsu)
2025-02-26 20:33 ` Ira Weiny
2025-02-26 22:19 ` Alison Schofield [this message]
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