Re: [PATCH] cxl/test: Define a CFMWS capable of a 3 way HB interleave

["Zhijian Li (Fujitsu)" <lizhijian@fujitsu.com>]

On 25/02/2025 07:50, alison.schofield@intel.com wrote:
> From: Alison Schofield <alison.schofield@intel.com>
> 
> The CXL unit test cxl-xor-region.sh is skipping a 1+1+1 region
> interleave test case because the window is not defined.
> 
> Additionally, upcoming expansion of 3 way HB interleave test cases
> (like 2+2+2) require the same window.
> 
> Replace an unused CFMWS with a 3-way capable CFMWS in the set of
> CFMWS's loaded when interleave_arithmetic=1.
> 
> Signed-off-by: Alison Schofield <alison.schofield@intel.com>

Tested-by: Li Zhijian <lizhijian@fujitsu.com>


> ---
>   tools/testing/cxl/test/cxl.c | 8 ++++----
>   1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/tools/testing/cxl/test/cxl.c b/tools/testing/cxl/test/cxl.c
> index 083a66a52731..e5cd874614d2 100644
> --- a/tools/testing/cxl/test/cxl.c
> +++ b/tools/testing/cxl/test/cxl.c
> @@ -331,14 +331,14 @@ static struct {
>   				.length = sizeof(mock_cedt.cfmws8),
>   			},
>   			.interleave_arithmetic = ACPI_CEDT_CFMWS_ARITHMETIC_XOR,
> -			.interleave_ways = 2,
> -			.granularity = 0,
> +			.interleave_ways = 8,
> +			.granularity = 1,
>   			.restrictions = ACPI_CEDT_CFMWS_RESTRICT_TYPE3 |
>   					ACPI_CEDT_CFMWS_RESTRICT_PMEM,
>   			.qtg_id = FAKE_QTG_ID,
> -			.window_size = SZ_256M * 16UL,
> +			.window_size = SZ_512M * 6UL,
>   		},
> -		.target = { 0, 1, 0, 1, },
> +		.target = { 0, 1, 2, },
>   	},
>   	.cxims0 = {
>   		.cxims = {
> 
> base-commit: 2bb67004903cfd35710750654669a77e7223fcd1