* [PATCH] cxl/test: Define a CFMWS capable of a 3 way HB interleave
@ 2025-02-24 23:50 alison.schofield
2025-02-25 0:27 ` Dave Jiang
` (2 more replies)
0 siblings, 3 replies; 5+ messages in thread
From: alison.schofield @ 2025-02-24 23:50 UTC (permalink / raw)
To: Davidlohr Bueso, Jonathan Cameron, Dave Jiang, Alison Schofield,
Vishal Verma, Ira Weiny, Dan Williams
Cc: linux-cxl
From: Alison Schofield <alison.schofield@intel.com>
The CXL unit test cxl-xor-region.sh is skipping a 1+1+1 region
interleave test case because the window is not defined.
Additionally, upcoming expansion of 3 way HB interleave test cases
(like 2+2+2) require the same window.
Replace an unused CFMWS with a 3-way capable CFMWS in the set of
CFMWS's loaded when interleave_arithmetic=1.
Signed-off-by: Alison Schofield <alison.schofield@intel.com>
---
tools/testing/cxl/test/cxl.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/tools/testing/cxl/test/cxl.c b/tools/testing/cxl/test/cxl.c
index 083a66a52731..e5cd874614d2 100644
--- a/tools/testing/cxl/test/cxl.c
+++ b/tools/testing/cxl/test/cxl.c
@@ -331,14 +331,14 @@ static struct {
.length = sizeof(mock_cedt.cfmws8),
},
.interleave_arithmetic = ACPI_CEDT_CFMWS_ARITHMETIC_XOR,
- .interleave_ways = 2,
- .granularity = 0,
+ .interleave_ways = 8,
+ .granularity = 1,
.restrictions = ACPI_CEDT_CFMWS_RESTRICT_TYPE3 |
ACPI_CEDT_CFMWS_RESTRICT_PMEM,
.qtg_id = FAKE_QTG_ID,
- .window_size = SZ_256M * 16UL,
+ .window_size = SZ_512M * 6UL,
},
- .target = { 0, 1, 0, 1, },
+ .target = { 0, 1, 2, },
},
.cxims0 = {
.cxims = {
base-commit: 2bb67004903cfd35710750654669a77e7223fcd1
--
2.37.3
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH] cxl/test: Define a CFMWS capable of a 3 way HB interleave
2025-02-24 23:50 [PATCH] cxl/test: Define a CFMWS capable of a 3 way HB interleave alison.schofield
@ 2025-02-25 0:27 ` Dave Jiang
2025-02-26 7:22 ` Zhijian Li (Fujitsu)
2025-02-26 20:33 ` Ira Weiny
2 siblings, 0 replies; 5+ messages in thread
From: Dave Jiang @ 2025-02-25 0:27 UTC (permalink / raw)
To: alison.schofield, Davidlohr Bueso, Jonathan Cameron, Vishal Verma,
Ira Weiny, Dan Williams
Cc: linux-cxl
On 2/24/25 4:50 PM, alison.schofield@intel.com wrote:
> From: Alison Schofield <alison.schofield@intel.com>
>
> The CXL unit test cxl-xor-region.sh is skipping a 1+1+1 region
> interleave test case because the window is not defined.
>
> Additionally, upcoming expansion of 3 way HB interleave test cases
> (like 2+2+2) require the same window.
>
> Replace an unused CFMWS with a 3-way capable CFMWS in the set of
> CFMWS's loaded when interleave_arithmetic=1.
>
> Signed-off-by: Alison Schofield <alison.schofield@intel.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
> ---
> tools/testing/cxl/test/cxl.c | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/tools/testing/cxl/test/cxl.c b/tools/testing/cxl/test/cxl.c
> index 083a66a52731..e5cd874614d2 100644
> --- a/tools/testing/cxl/test/cxl.c
> +++ b/tools/testing/cxl/test/cxl.c
> @@ -331,14 +331,14 @@ static struct {
> .length = sizeof(mock_cedt.cfmws8),
> },
> .interleave_arithmetic = ACPI_CEDT_CFMWS_ARITHMETIC_XOR,
> - .interleave_ways = 2,
> - .granularity = 0,
> + .interleave_ways = 8,
> + .granularity = 1,
> .restrictions = ACPI_CEDT_CFMWS_RESTRICT_TYPE3 |
> ACPI_CEDT_CFMWS_RESTRICT_PMEM,
> .qtg_id = FAKE_QTG_ID,
> - .window_size = SZ_256M * 16UL,
> + .window_size = SZ_512M * 6UL,
> },
> - .target = { 0, 1, 0, 1, },
> + .target = { 0, 1, 2, },
> },
> .cxims0 = {
> .cxims = {
>
> base-commit: 2bb67004903cfd35710750654669a77e7223fcd1
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] cxl/test: Define a CFMWS capable of a 3 way HB interleave
2025-02-24 23:50 [PATCH] cxl/test: Define a CFMWS capable of a 3 way HB interleave alison.schofield
2025-02-25 0:27 ` Dave Jiang
@ 2025-02-26 7:22 ` Zhijian Li (Fujitsu)
2025-02-26 20:33 ` Ira Weiny
2 siblings, 0 replies; 5+ messages in thread
From: Zhijian Li (Fujitsu) @ 2025-02-26 7:22 UTC (permalink / raw)
To: alison.schofield@intel.com, Davidlohr Bueso, Jonathan Cameron,
Dave Jiang, Vishal Verma, Ira Weiny, Dan Williams
Cc: linux-cxl@vger.kernel.org
On 25/02/2025 07:50, alison.schofield@intel.com wrote:
> From: Alison Schofield <alison.schofield@intel.com>
>
> The CXL unit test cxl-xor-region.sh is skipping a 1+1+1 region
> interleave test case because the window is not defined.
>
> Additionally, upcoming expansion of 3 way HB interleave test cases
> (like 2+2+2) require the same window.
>
> Replace an unused CFMWS with a 3-way capable CFMWS in the set of
> CFMWS's loaded when interleave_arithmetic=1.
>
> Signed-off-by: Alison Schofield <alison.schofield@intel.com>
Tested-by: Li Zhijian <lizhijian@fujitsu.com>
> ---
> tools/testing/cxl/test/cxl.c | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/tools/testing/cxl/test/cxl.c b/tools/testing/cxl/test/cxl.c
> index 083a66a52731..e5cd874614d2 100644
> --- a/tools/testing/cxl/test/cxl.c
> +++ b/tools/testing/cxl/test/cxl.c
> @@ -331,14 +331,14 @@ static struct {
> .length = sizeof(mock_cedt.cfmws8),
> },
> .interleave_arithmetic = ACPI_CEDT_CFMWS_ARITHMETIC_XOR,
> - .interleave_ways = 2,
> - .granularity = 0,
> + .interleave_ways = 8,
> + .granularity = 1,
> .restrictions = ACPI_CEDT_CFMWS_RESTRICT_TYPE3 |
> ACPI_CEDT_CFMWS_RESTRICT_PMEM,
> .qtg_id = FAKE_QTG_ID,
> - .window_size = SZ_256M * 16UL,
> + .window_size = SZ_512M * 6UL,
> },
> - .target = { 0, 1, 0, 1, },
> + .target = { 0, 1, 2, },
> },
> .cxims0 = {
> .cxims = {
>
> base-commit: 2bb67004903cfd35710750654669a77e7223fcd1
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] cxl/test: Define a CFMWS capable of a 3 way HB interleave
2025-02-24 23:50 [PATCH] cxl/test: Define a CFMWS capable of a 3 way HB interleave alison.schofield
2025-02-25 0:27 ` Dave Jiang
2025-02-26 7:22 ` Zhijian Li (Fujitsu)
@ 2025-02-26 20:33 ` Ira Weiny
2025-02-26 22:19 ` Alison Schofield
2 siblings, 1 reply; 5+ messages in thread
From: Ira Weiny @ 2025-02-26 20:33 UTC (permalink / raw)
To: alison.schofield, Davidlohr Bueso, Jonathan Cameron, Dave Jiang,
Vishal Verma, Ira Weiny, Dan Williams
Cc: linux-cxl
alison.schofield@ wrote:
> From: Alison Schofield <alison.schofield@intel.com>
>
> The CXL unit test cxl-xor-region.sh is skipping a 1+1+1 region
> interleave test case because the window is not defined.
>
> Additionally, upcoming expansion of 3 way HB interleave test cases
> (like 2+2+2) require the same window.
>
> Replace an unused CFMWS with a 3-way capable CFMWS in the set of
> CFMWS's loaded when interleave_arithmetic=1.
>
> Signed-off-by: Alison Schofield <alison.schofield@intel.com>
> ---
> tools/testing/cxl/test/cxl.c | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/tools/testing/cxl/test/cxl.c b/tools/testing/cxl/test/cxl.c
> index 083a66a52731..e5cd874614d2 100644
> --- a/tools/testing/cxl/test/cxl.c
> +++ b/tools/testing/cxl/test/cxl.c
> @@ -331,14 +331,14 @@ static struct {
> .length = sizeof(mock_cedt.cfmws8),
> },
> .interleave_arithmetic = ACPI_CEDT_CFMWS_ARITHMETIC_XOR,
> - .interleave_ways = 2,
> - .granularity = 0,
> + .interleave_ways = 8,
> + .granularity = 1,
> .restrictions = ACPI_CEDT_CFMWS_RESTRICT_TYPE3 |
> ACPI_CEDT_CFMWS_RESTRICT_PMEM,
> .qtg_id = FAKE_QTG_ID,
> - .window_size = SZ_256M * 16UL,
> + .window_size = SZ_512M * 6UL,
> },
> - .target = { 0, 1, 0, 1, },
> + .target = { 0, 1, 2, },
Minor nit:
Reviewed-by: Ira Weiny <ira.weiny@intel.com>
Should this also include:
diff --git a/tools/testing/cxl/test/cxl.c b/tools/testing/cxl/test/cxl.c
index cc8948f49117..f0b5b7b8d1d0 100644
--- a/tools/testing/cxl/test/cxl.c
+++ b/tools/testing/cxl/test/cxl.c
@@ -155,7 +155,7 @@ static struct {
} cfmws7;
struct {
struct acpi_cedt_cfmws cfmws;
- u32 target[4];
+ u32 target[3];
} cfmws8;
struct {
struct acpi_cedt_cxims cxims;
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH] cxl/test: Define a CFMWS capable of a 3 way HB interleave
2025-02-26 20:33 ` Ira Weiny
@ 2025-02-26 22:19 ` Alison Schofield
0 siblings, 0 replies; 5+ messages in thread
From: Alison Schofield @ 2025-02-26 22:19 UTC (permalink / raw)
To: Ira Weiny
Cc: Davidlohr Bueso, Jonathan Cameron, Dave Jiang, Vishal Verma,
Dan Williams, linux-cxl
On Wed, Feb 26, 2025 at 02:33:14PM -0600, Ira Weiny wrote:
> alison.schofield@ wrote:
> > From: Alison Schofield <alison.schofield@intel.com>
> >
> > The CXL unit test cxl-xor-region.sh is skipping a 1+1+1 region
> > interleave test case because the window is not defined.
> >
> > Additionally, upcoming expansion of 3 way HB interleave test cases
> > (like 2+2+2) require the same window.
> >
> > Replace an unused CFMWS with a 3-way capable CFMWS in the set of
> > CFMWS's loaded when interleave_arithmetic=1.
> >
> > Signed-off-by: Alison Schofield <alison.schofield@intel.com>
> > ---
> > tools/testing/cxl/test/cxl.c | 8 ++++----
> > 1 file changed, 4 insertions(+), 4 deletions(-)
> >
> > diff --git a/tools/testing/cxl/test/cxl.c b/tools/testing/cxl/test/cxl.c
> > index 083a66a52731..e5cd874614d2 100644
> > --- a/tools/testing/cxl/test/cxl.c
> > +++ b/tools/testing/cxl/test/cxl.c
> > @@ -331,14 +331,14 @@ static struct {
> > .length = sizeof(mock_cedt.cfmws8),
> > },
> > .interleave_arithmetic = ACPI_CEDT_CFMWS_ARITHMETIC_XOR,
> > - .interleave_ways = 2,
> > - .granularity = 0,
> > + .interleave_ways = 8,
> > + .granularity = 1,
> > .restrictions = ACPI_CEDT_CFMWS_RESTRICT_TYPE3 |
> > ACPI_CEDT_CFMWS_RESTRICT_PMEM,
> > .qtg_id = FAKE_QTG_ID,
> > - .window_size = SZ_256M * 16UL,
> > + .window_size = SZ_512M * 6UL,
> > },
> > - .target = { 0, 1, 0, 1, },
> > + .target = { 0, 1, 2, },
>
> Minor nit:
Not a nit. Thanks, revving!
>
> Reviewed-by: Ira Weiny <ira.weiny@intel.com>
>
> Should this also include:
>
> diff --git a/tools/testing/cxl/test/cxl.c b/tools/testing/cxl/test/cxl.c
> index cc8948f49117..f0b5b7b8d1d0 100644
> --- a/tools/testing/cxl/test/cxl.c
> +++ b/tools/testing/cxl/test/cxl.c
> @@ -155,7 +155,7 @@ static struct {
> } cfmws7;
> struct {
> struct acpi_cedt_cfmws cfmws;
> - u32 target[4];
> + u32 target[3];
> } cfmws8;
> struct {
> struct acpi_cedt_cxims cxims;
^ permalink raw reply [flat|nested] 5+ messages in thread
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2025-02-24 23:50 [PATCH] cxl/test: Define a CFMWS capable of a 3 way HB interleave alison.schofield
2025-02-25 0:27 ` Dave Jiang
2025-02-26 7:22 ` Zhijian Li (Fujitsu)
2025-02-26 20:33 ` Ira Weiny
2025-02-26 22:19 ` Alison Schofield
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