Re: [PATCH] cxl/hdm: Extend DVSEC range register emulation for region enumeration

[Gregory Price <gregory.price@memverge.com>]

On Wed, Mar 29, 2023 at 11:33:05PM -0700, Dan Williams wrote:
> Gregory Price wrote:
> > On Wed, Mar 29, 2023 at 09:21:25PM -0700, Dan Williams wrote:
> > > > Is the DVSEC Range Register expected to be programmed by bios, and are
> > > > not being programmed correctly?
> > > 
> > > This debug experiment makes me think perhaps the *device* is at fault,
> > > not the BIOS. Perhaps the device accepts writes to CXL_DVSEC_RANGE_BASE
> > > to set up the decode as expected, but reads return 0? That's the only
> > > way that I can see that forcing that offset results in successfully
> > > talking to memory.
> > > 
> > 
> > Oh, i meant to add that i tested whether the memory is accessible via
> > numactl --membind=1 with both memhog and a python prompt, and things
> > worked just fine.  So memory works.
> 
> One other theory is that the device is correct, but the platform CXL
> window accepts transactions at an offset and then removes that offset
> when transmitting the address down the CXL port. So device thinks its
> decoding 0x0 and never sees the offset removed by the host bridge.

Wouldn't that be against the spec?  I thought the device intended to
receive HPA and do its decode accordingly.

Otherwise you could have multiple devices programmed capable of decoding
0x0, which is already the device address, so there's nothing to
"decode".

I'll follow up as I learn more, this is concerning.  Certainly explains
why every time I switch hardware nothing seems to work quite right.

~Gregory