From: Robert Richter <rrichter@amd.com>
To: kernel test robot <lkp@intel.com>
Cc: Terry Bowman <terry.bowman@amd.com>, <alison.schofield@intel.com>,
<vishal.l.verma@intel.com>, <ira.weiny@intel.com>,
<bwidawsk@kernel.org>, <dan.j.williams@intel.com>,
<dave.jiang@intel.com>, <Jonathan.Cameron@huawei.com>,
<linux-cxl@vger.kernel.org>, <oe-kbuild-all@lists.linux.dev>,
<linux-kernel@vger.kernel.org>, <bhelgaas@google.com>
Subject: Re: [PATCH v4 13/23] cxl/hdm: Use stored Component Register mappings to map HDM decoder capability
Date: Wed, 24 May 2023 11:49:22 +0200 [thread overview]
Message-ID: <ZG3cpEj9k8S9DMAA@rric.localdomain> (raw)
In-Reply-To: <202305240842.zr8PTfcu-lkp@intel.com>
On 24.05.23 09:12:24, kernel test robot wrote:
> >> drivers/cxl/core/hdm.c:128:26: warning: no previous prototype for 'cxl_port_get_comp_map' [-Wmissing-prototypes]
> 128 | struct cxl_register_map *cxl_port_get_comp_map(struct cxl_port *port)
> | ^~~~~~~~~~~~~~~~~~~~~
>
>
> vim +/cxl_port_get_comp_map +128 drivers/cxl/core/hdm.c
>
> 127
> > 128 struct cxl_register_map *cxl_port_get_comp_map(struct cxl_port *port)
This should have been 'static' and also solves the warning then. Will
change.
-Robert
> 129 {
> 130 /*
> 131 * HDM capability applies to Endpoints, USPs and VH Host
> 132 * Bridges. The Endpoint's component register mappings are
> 133 * located in the cxlds.
> 134 */
> 135 if (is_cxl_endpoint(port)) {
> 136 struct cxl_memdev *memdev = to_cxl_memdev(port->uport);
> 137
> 138 return &memdev->cxlds->comp_map;
> 139 }
> 140
> 141 return &port->comp_map;
> 142 }
> 143
next prev parent reply other threads:[~2023-05-24 9:49 UTC|newest]
Thread overview: 68+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-23 23:21 [PATCH v4 00/23] cxl/pci: Add support for RCH RAS error handling Terry Bowman
2023-05-23 23:21 ` [PATCH v4 01/23] cxl/acpi: Probe RCRB later during RCH downstream port creation Terry Bowman
2023-06-01 10:13 ` Jonathan Cameron
2023-06-02 14:16 ` Robert Richter
2023-05-23 23:21 ` [PATCH v4 02/23] cxl/rch: Prepare for caching the MMIO mapped PCIe AER capability Terry Bowman
2023-06-01 10:38 ` Jonathan Cameron
2023-06-02 14:53 ` Robert Richter
2023-05-23 23:21 ` [PATCH v4 03/23] cxl: Rename member @dport of struct cxl_dport to @dev Terry Bowman
2023-06-01 10:41 ` Jonathan Cameron
2023-05-23 23:21 ` [PATCH v4 04/23] cxl/core/regs: Add @dev to cxl_register_map Terry Bowman
2023-06-01 10:49 ` Jonathan Cameron
2023-06-02 15:11 ` Robert Richter
2023-05-23 23:21 ` [PATCH v4 05/23] cxl/pci: Refactor component register discovery for reuse Terry Bowman
2023-06-01 10:52 ` Jonathan Cameron
2023-05-23 23:21 ` [PATCH v4 06/23] cxl/acpi: Moving add_host_bridge_uport() around Terry Bowman
2023-06-01 10:54 ` Jonathan Cameron
2023-05-23 23:21 ` [PATCH v4 07/23] cxl/acpi: Directly bind the CEDT detected CHBCR to the Host Bridge's port Terry Bowman
2023-06-01 12:45 ` Jonathan Cameron
2023-06-02 15:42 ` Robert Richter
2023-05-23 23:21 ` [PATCH v4 08/23] cxl/regs: Remove early capability checks in Component Register setup Terry Bowman
2023-06-01 12:49 ` Jonathan Cameron
2023-05-23 23:22 ` [PATCH v4 09/23] cxl/pci: Early setup RCH dport component registers from RCRB Terry Bowman
2023-06-01 12:59 ` Jonathan Cameron
2023-06-02 15:45 ` Robert Richter
2023-05-23 23:22 ` [PATCH v4 10/23] cxl/port: Store the port's Component Register mappings in struct cxl_port Terry Bowman
2023-06-01 13:06 ` Jonathan Cameron
2023-06-02 15:58 ` Robert Richter
2023-05-23 23:22 ` [PATCH v4 11/23] cxl/port: Store the downstream port's Component Register mappings in struct cxl_dport Terry Bowman
2023-06-01 13:07 ` Jonathan Cameron
2023-05-23 23:22 ` [PATCH v4 12/23] cxl/pci: Store the endpoint's Component Register mappings in struct cxl_dev_state Terry Bowman
2023-06-01 13:07 ` Jonathan Cameron
2023-05-23 23:22 ` [PATCH v4 13/23] cxl/hdm: Use stored Component Register mappings to map HDM decoder capability Terry Bowman
[not found] ` <202305240842.zr8PTfcu-lkp@intel.com>
2023-05-24 9:49 ` Robert Richter [this message]
2023-06-01 13:11 ` Jonathan Cameron
2023-05-23 23:22 ` [PATCH v4 14/23] cxl/port: Remove Component Register base address from struct cxl_port Terry Bowman
2023-06-01 13:27 ` Jonathan Cameron
2023-05-23 23:22 ` [PATCH v4 15/23] cxl/port: Remove Component Register base address from struct cxl_dport Terry Bowman
2023-06-01 13:28 ` Jonathan Cameron
2023-05-23 23:22 ` [PATCH v4 16/23] cxl/pci: Remove Component Register base address from struct cxl_dev_state Terry Bowman
2023-06-01 13:28 ` Jonathan Cameron
2023-05-23 23:22 ` [PATCH v4 17/23] cxl/pci: Add RCH downstream port AER register discovery Terry Bowman
2023-06-01 13:36 ` Jonathan Cameron
2023-06-01 13:38 ` Jonathan Cameron
2023-05-23 23:22 ` [PATCH v4 18/23] PCI/AER: Refactor cper_print_aer() for use by CXL driver module Terry Bowman
2023-05-24 16:55 ` Bjorn Helgaas
2023-05-25 21:38 ` Terry Bowman
2023-05-23 23:22 ` [PATCH v4 19/23] cxl/pci: Update CXL error logging to use RAS register address Terry Bowman
2023-06-01 13:42 ` Jonathan Cameron
2023-05-23 23:22 ` [PATCH v4 20/23] cxl/pci: Prepare for logging RCH downstream port protocol errors Terry Bowman
2023-06-01 13:49 ` Jonathan Cameron
2023-06-01 14:06 ` Terry Bowman
2023-06-01 14:12 ` Jonathan Cameron
2023-05-23 23:22 ` [PATCH v4 21/23] cxl/pci: Add RCH downstream port error logging Terry Bowman
2023-06-01 14:03 ` Jonathan Cameron
2023-05-23 23:22 ` [PATCH v4 22/23] PCI/AER: Forward RCH downstream port-detected errors to the CXL.mem dev handler Terry Bowman
2023-05-24 21:32 ` Bjorn Helgaas
2023-05-25 21:29 ` Robert Richter
2023-05-25 22:01 ` Bjorn Helgaas
2023-05-25 22:28 ` Robert Richter
2023-06-01 14:06 ` Jonathan Cameron
2023-05-23 23:22 ` [PATCH v4 23/23] PCI/AER: Unmask RCEC internal errors to enable RCH downstream port error handling Terry Bowman
2023-05-24 21:45 ` Bjorn Helgaas
2023-05-25 22:08 ` Robert Richter
2023-05-26 20:31 ` Bjorn Helgaas
2023-06-01 14:11 ` Jonathan Cameron
2023-06-02 16:41 ` Robert Richter
2023-05-23 23:29 ` [PATCH v4 00/23] cxl/pci: Add support for RCH RAS error handling - CHANGELOG Terry Bowman
2023-05-24 1:39 ` [PATCH v4 00/23] cxl/pci: Add support for RCH RAS error handling Terry Bowman
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