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From: Robert Richter <rrichter@amd.com>
To: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Davidlohr Bueso <dave@stgolabs.net>,
	Dave Jiang <dave.jiang@intel.com>,
	Alison Schofield <alison.schofield@intel.com>,
	Vishal Verma <vishal.l.verma@intel.com>,
	Ira Weiny <ira.weiny@intel.com>,
	Ben Widawsky <bwidawsk@kernel.org>,
	Dan Williams <dan.j.williams@intel.com>,
	linux-cxl@vger.kernel.org, linux-kernel@vger.kernel.org,
	Bjorn Helgaas <bhelgaas@google.com>,
	Terry Bowman <terry.bowman@amd.com>
Subject: Re: [PATCH v12 10/20] cxl/pci: Introduce config option PCIEAER_CXL
Date: Sat, 21 Oct 2023 00:36:39 +0200	[thread overview]
Message-ID: <ZTMA9xQTAMIifnTA@rric.localdomain> (raw)
In-Reply-To: <20231019153045.000038cc@Huawei.com>

Jon,

On 19.10.23 15:30:45, Jonathan Cameron wrote:
> On Wed, 18 Oct 2023 19:17:03 +0200
> Robert Richter <rrichter@amd.com> wrote:
> 
> > CXL error handling depends on AER.
> > 
> > Introduce config option PCIEAER_CXL in preparation of the AER dport
> > error handling. Also, introduce the stub function
> > devm_cxl_setup_parent_dport() to setup dports.
> > 
> > This is in preparation of follow on patches.
> > 
> > Note the Kconfg part of the option is added in a later patch to enable
> > it once coding of the feature is complete.
> > 
> > Signed-off-by: Robert Richter <rrichter@amd.com>
> LGTM
> 
> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>

many thanks for all your instant reviews of that series, that helped a
lot.

-Robert

  reply	other threads:[~2023-10-20 22:36 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-10-18 17:16 [PATCH v12 00/20] cxl/pci: Add support for RCH RAS error handling Robert Richter
2023-10-18 17:16 ` [PATCH v12 01/20] cxl/port: Fix release of RCD endpoints Robert Richter
2023-10-27  3:46   ` Dan Williams
2023-10-27 22:55     ` Robert Richter
2023-10-28  0:32       ` Dan Williams
2023-10-28  1:39         ` Dan Williams
2023-10-29 16:17           ` Robert Richter
2023-10-18 17:16 ` [PATCH v12 02/20] cxl/core/regs: Rename @dev to @host in struct cxl_register_map Robert Richter
2023-10-27 20:04   ` Dan Williams
2023-10-18 17:16 ` [PATCH v12 03/20] cxl/port: Fix @host confusion in cxl_dport_setup_regs() Robert Richter
2023-10-18 17:16 ` [PATCH v12 04/20] cxl/port: Rename @comp_map to @reg_map in struct cxl_register_map Robert Richter
2023-10-18 17:16 ` [PATCH v12 05/20] cxl/port: Pre-initialize component register mappings Robert Richter
2023-10-18 17:16 ` [PATCH v12 06/20] cxl/pci: Store the endpoint's Component Register mappings in struct cxl_dev_state Robert Richter
2023-10-18 17:17 ` [PATCH v12 07/20] cxl/hdm: Use stored Component Register mappings to map HDM decoder capability Robert Richter
2023-10-27 21:51   ` Dan Williams
2023-10-18 17:17 ` [PATCH v12 08/20] cxl/pci: Remove Component Register base address from struct cxl_dev_state Robert Richter
2023-10-27 21:54   ` Dan Williams
2023-10-18 17:17 ` [PATCH v12 09/20] cxl/port: Remove Component Register base address from struct cxl_port Robert Richter
2023-10-18 17:17 ` [PATCH v12 10/20] cxl/pci: Introduce config option PCIEAER_CXL Robert Richter
2023-10-19 14:30   ` Jonathan Cameron
2023-10-20 22:36     ` Robert Richter [this message]
2023-10-27 22:02   ` Dan Williams
2023-10-18 17:17 ` [PATCH v12 11/20] cxl/pci: Add RCH downstream port AER register discovery Robert Richter
2023-10-27 22:12   ` Dan Williams
2023-10-18 17:17 ` [PATCH v12 12/20] PCI/AER: Refactor cper_print_aer() for use by CXL driver module Robert Richter
2023-10-18 17:17 ` [PATCH v12 13/20] cxl/pci: Update CXL error logging to use RAS register address Robert Richter
2023-10-18 17:17 ` [PATCH v12 14/20] cxl/pci: Map RCH downstream AER registers for logging protocol errors Robert Richter
2023-10-27 22:16   ` Dan Williams
2023-10-28  3:23     ` Dan Williams
2023-10-18 17:17 ` [PATCH v12 15/20] cxl/pci: Add RCH downstream port error logging Robert Richter
2023-10-18 17:17 ` [PATCH v12 16/20] cxl/pci: Disable root port interrupts in RCH mode Robert Richter
2023-10-18 17:17 ` [PATCH v12 17/20] PCI/AER: Forward RCH downstream port-detected errors to the CXL.mem dev handler Robert Richter
2023-10-18 17:17 ` [PATCH v12 18/20] PCI/AER: Unmask RCEC internal errors to enable RCH downstream port error handling Robert Richter
2023-10-18 17:17 ` [PATCH v12 19/20] cxl/core/regs: Rename phys_addr in cxl_map_component_regs() Robert Richter
2023-10-18 17:17 ` [PATCH v12 20/20] cxl/core/regs: Rework cxl_map_pmu_regs() to use map->dev for devm Robert Richter

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