From: Alison Schofield <alison.schofield@intel.com>
To: Dave Jiang <dave.jiang@intel.com>
Cc: <linux-cxl@vger.kernel.org>, <dave@stgolabs.net>,
<jonathan.cameron@huawei.com>, <vishal.l.verma@intel.com>,
<ira.weiny@intel.com>, <dan.j.williams@intel.com>,
<rrichter@amd.com>
Subject: Re: [PATCH v9 04/10] cxl: Move port register setup to first dport appear
Date: Tue, 9 Sep 2025 19:21:09 -0700 [thread overview]
Message-ID: <aMDglXCRLDzk4KxA@aschofie-mobl2.lan> (raw)
In-Reply-To: <20250829180928.842707-5-dave.jiang@intel.com>
On Fri, Aug 29, 2025 at 11:09:22AM -0700, Dave Jiang wrote:
> This patch moves the port register setup to when the first dport appears
> via the memdev probe path. At this point, the CXL link should be
> established and the register access is expected to succeed. This change
> addresses an error message observed when PCIe hotplug is enabled on
> an Intel platform. The error messages "cxl portN: Couldn't locate the
> CXL.cache and CXL.mem capability array header" is observed for the
> hostbridge during cxl_acpi driver probe. If the cxl_acpi module
> probe is running before the CXL link between the endpoint device and the
> RP is established, then the platform may not have exposed DVSEC ID 3
> and/or DVSEC ID 7 blocks which will trigger the error message. This
> behavior is defined by the spec and not a hardware quirk.
>
> This change also needs the dport enumeration to be moved to the memdev
> probe path in order to address the issue. This change is just part of
> the code refactoring and is not a wholly contained fix itself.
Reviewed-by: Alison Schofield <alison.schofield@intel.com>
next prev parent reply other threads:[~2025-09-10 2:21 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-29 18:09 [PATCH v9 00/10] cxl: Delay HB port and switch dport probing until endpoint dev probe Dave Jiang
2025-08-29 18:09 ` [PATCH v9 01/10] cxl: Add helper to detect top of CXL device topology Dave Jiang
2025-08-29 18:09 ` [PATCH v9 02/10] cxl: Add helper to reap dport Dave Jiang
2025-09-15 9:42 ` Robert Richter
2025-08-29 18:09 ` [PATCH v9 03/10] cxl: Add a cached copy of target_map to cxl_decoder Dave Jiang
2025-09-10 2:22 ` Alison Schofield
2025-09-15 10:29 ` Robert Richter
2025-08-29 18:09 ` [PATCH v9 04/10] cxl: Move port register setup to first dport appear Dave Jiang
2025-09-10 2:21 ` Alison Schofield [this message]
2025-08-29 18:09 ` [PATCH v9 05/10] cxl/test: Refactor decoder setup to reduce cxl_test burden Dave Jiang
2025-09-09 15:44 ` Jonathan Cameron
2025-09-10 2:19 ` Alison Schofield
2025-09-18 9:18 ` Robert Richter
2025-08-29 18:09 ` [PATCH v9 06/10] cxl: Defer dport allocation for switch ports Dave Jiang
2025-09-09 15:56 ` Jonathan Cameron
2025-09-10 0:53 ` Alison Schofield
2025-08-29 18:09 ` [PATCH v9 07/10] cxl/test: Add mock version of devm_cxl_add_dport_by_dev() Dave Jiang
2025-08-29 18:09 ` [PATCH v9 08/10] cxl/test: Adjust the mock version of devm_cxl_switch_port_decoders_setup() Dave Jiang
2025-09-09 15:57 ` Jonathan Cameron
2025-09-10 0:48 ` Alison Schofield
2025-08-29 18:09 ` [PATCH v9 09/10] cxl/test: Setup target_map for cxl_test decoder initialization Dave Jiang
2025-09-10 0:27 ` Alison Schofield
2025-08-29 18:09 ` [PATCH v9 10/10] cxl: Change sslbis handler to only handle single dport Dave Jiang
2025-09-17 17:28 ` [PATCH v9 00/10] cxl: Delay HB port and switch dport probing until endpoint dev probe Dave Jiang
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