Re: [RFC QEMU PATCH v4 2/2] pci-host/cxl: Support creation of a new CXL Host Bridge

[Yuquan Wang <wangyuquan1236@phytium.com.cn>]

Wed, Sep 17, 2025 at 05:37:42PM +0100, Jonathan Cameron wrote:
> On Thu, 7 Aug 2025 18:59:10 +0800
> wangyuquan <wangyuquan1236@phytium.com.cn> wrote:
> 
> > From: Yuquan Wang <wangyuquan1236@phytium.com.cn>
> > 
> > Define a new CXL host bridge type (TYPE_CXL_HOST). This is an
> > independent CXL host bridge which combined GPEX features (ECAM, MMIO
> > windows and irq) and CXL Host Bridge Component Registers (CHBCR).
> > 
> > The root bus path of CXL_HOST is "0001:00", that would not affect the
> > original PCIe host topology on some platforms. In the previous, the
> > pxb-cxl-host with any CXL root ports and CXL endpoint devices would
> > share the resources (like BDF, MMIO space) of the original pcie
> > domain, but it would cause some platforms like sbsa-ref are unable to
> > support the original number of PCIe devices. The new type provides a
> > solution to resolve the problem.
> > 
> > Signed-off-by: Yuquan Wang <wangyuquan1236@phytium.com.cn>
> 
> Likewise, this looks fine to me.  If the SBSA maintainers
> are happy with the approach and PCI folk think the more generic parts
> look fine then would be good to move this forwards.
> 
> Acked-by: Jonathan Cameron <jonathan.cameron@huawei.com>
>

Thanks for reviewing! I am very much looking forward to the maintainer of
PCI continuing to review this patch and providing relevant comments.

Yuquan