[NDCTL PATCH] cxl: Add CXL type2 accelerator unit test

[NDCTL PATCH] cxl: Add CXL type2 accelerator unit test

[Dave Jiang]

CXL type2 hierachy can be setup via the cxl_test. Add a regression test
unit to CXL CLI to verify the type2 loading/unloading. Test include
removing the root port and bringing it back as well as unbinding the
type2 mock device driver and bringing it back. The expectation is that
the auto region should return.

Signed-off-by: Dave Jiang <dave.jiang@intel.com>
---
 test/cxl-type2.sh | 71 +++++++++++++++++++++++++++++++++++++++++++++++
 test/meson.build  |  2 ++
 2 files changed, 73 insertions(+)
 create mode 100644 test/cxl-type2.sh

diff --git a/test/cxl-type2.sh b/test/cxl-type2.sh
new file mode 100644
index 000000000000..0ece0c4f6ddb
--- /dev/null
+++ b/test/cxl-type2.sh
@@ -0,0 +1,71 @@
+#!/bin/bash
+# SPDX-License-Identifier: GPL-2.0
+# Copyright (C) 2026 Intel Corporation. All rights reserved.
+
+. "$(dirname "$0")"/common
+
+rc=77
+
+set -ex
+
+trap 'err $LINENO' ERR
+
+check_prereq "jq"
+
+remove_kmod() {
+	modprobe -r cxl_test
+}
+
+load_kmod() {
+	modprobe cxl_test type2_test=1
+}
+
+init_check() {
+	load_kmod
+	[ -f /sys/module/cxl_test/parameters/type2_test ] || \
+		do_skip "cxl_test type2_test module param not available"
+	region=$("$CXL" list -b cxl_test -R | jq -r '.[0].region')
+	[ -n "$region" ] || err "$LINENO"
+	check_dmesg "$LINENO"
+	remove_kmod
+}
+
+# Test rootport disable/enable case
+cycle_root_port() {
+	load_kmod
+	port=$("$CXL" list -b cxl_test -P | jq -r '.[0].port')
+	[ -n "$port" ] || err "$LINENO"
+
+	"$CXL" disable-port "$port" -f
+	region=$(cxl list -b cxl_test -R | jq -r '.[0].region // empty')
+	[ -z "$region" ] || err "$LINENO"
+
+	"$CXL" enable-port "$port"
+	echo cxl_type2_accel.0 > /sys/bus/platform/drivers/cxl_mock_accel/bind
+	region=$(cxl list -b cxl_test -R | jq -r '.[0].region')
+	[ -n "$region" ] || err "$LINENO"
+	check_dmesg "$LINENO"
+	remove_kmod
+}
+
+# Test reload firmware case
+cycle_pdev_driver() {
+	load_kmod
+	region=$("$CXL" list -b cxl_test -R | jq -r '.[0].region')
+	[ -n "$region" ] || err "$LINENO"
+	echo cxl_type2_accel.0 > /sys/bus/platform/drivers/cxl_mock_accel/unbind
+	region=$("$CXL" list -b cxl_test -R | jq -r '.[0].region // empty')
+	[ -z "$region" ] || err "$LINENO"
+	echo cxl_type2_accel.0 > /sys/bus/platform/drivers/cxl_mock_accel/bind
+	region=$("$CXL" list -b cxl_test -R | jq -r '.[0].region')
+	[ -n "$region" ] || err "$LINENO"
+	check_dmesg "$LINENO"
+	remove_kmod
+}
+
+remove_kmod
+rc=1
+
+init_check
+cycle_root_port
+cycle_pdev_driver
diff --git a/test/meson.build b/test/meson.build
index e0e2193bfd51..567347b655d2 100644
--- a/test/meson.build
+++ b/test/meson.build
@@ -171,6 +171,7 @@ cxl_translate = find_program('cxl-translate.sh')
 cxl_elc = find_program('cxl-elc.sh')
 cxl_dax_hmem = find_program('cxl-dax-hmem.sh')
 cxl_region_replay = find_program('cxl-region-replay.sh')
+cxl_type2 = find_program('cxl-type2.sh')
 
 tests = [
   [ 'libndctl',               libndctl,		  'ndctl' ],
@@ -207,6 +208,7 @@ tests = [
   [ 'cxl-elc.sh',             cxl_elc,            'cxl'   ],
   [ 'cxl-dax-hmem.sh',        cxl_dax_hmem,       'cxl'   ],
   [ 'cxl-region-replay.sh',   cxl_region_replay,  'cxl'   ],
+  [ 'cxl-type2.sh',           cxl_type2,          'cxl'   ],
 ]
 
 if get_option('destructive').enabled()

base-commit: 81c7cdd6cbcb4f1f77870ff02d8dd86298036f58
-- 
2.53.0

Re: [NDCTL PATCH] cxl: Add CXL type2 accelerator unit test

[Alison Schofield]

On Wed, Apr 22, 2026 at 04:08:33PM -0700, Dave Jiang wrote:
> CXL type2 hierachy can be setup via the cxl_test. Add a regression test
> unit to CXL CLI to verify the type2 loading/unloading. Test include
> removing the root port and bringing it back as well as unbinding the
> type2 mock device driver and bringing it back. The expectation is that
> the auto region should return.

I guess I'd like some words here about what is important to test, and
how much type2 we can test with the accel mock driver. This topology is
limited to an auto region with a single device which I believe matches
our kernel implementation.  BTW, is that spec limit or linux implementation
limit?

How about checking that it cannot be destroyed? That's one we've been
discussing for the kernel.

How about disable/enable memdev?

I'd like to see replay_region run here too. You've already set this up
as an autoregion, but running the replay_region means we've kept the
topology rebuild in tact.

I did run this test with your kernel branch.

More below...

> 
> Signed-off-by: Dave Jiang <dave.jiang@intel.com>
> ---
>  test/cxl-type2.sh | 71 +++++++++++++++++++++++++++++++++++++++++++++++
>  test/meson.build  |  2 ++
>  2 files changed, 73 insertions(+)
>  create mode 100644 test/cxl-type2.sh
> 
> diff --git a/test/cxl-type2.sh b/test/cxl-type2.sh
> new file mode 100644
> index 000000000000..0ece0c4f6ddb
> --- /dev/null
> +++ b/test/cxl-type2.sh
> @@ -0,0 +1,71 @@
> +#!/bin/bash
> +# SPDX-License-Identifier: GPL-2.0
> +# Copyright (C) 2026 Intel Corporation. All rights reserved.
> +
> +. "$(dirname "$0")"/common
> +
> +rc=77
> +
> +set -ex
> +
> +trap 'err $LINENO' ERR
> +
> +check_prereq "jq"
> +
> +remove_kmod() {
> +	modprobe -r cxl_test
> +}
> +
> +load_kmod() {
> +	modprobe cxl_test type2_test=1
> +}
> +
> +init_check() {
> +	load_kmod
> +	[ -f /sys/module/cxl_test/parameters/type2_test ] || \
> +		do_skip "cxl_test type2_test module param not available"
> +	region=$("$CXL" list -b cxl_test -R | jq -r '.[0].region')
> +	[ -n "$region" ] || err "$LINENO"
> +	check_dmesg "$LINENO"
> +	remove_kmod
> +}

This is different than other scripts, including the 3x load/unload
cycles and 3x the check_dmesg surface area. Unless you are looking
for something special in kernel log, and in that case we can look
for that specifically.

Suggest following the typical test pattern of:

check_prereq like you have, then:

unload
load
check for skip
rc=1  /* rc=1 after we pass the skip test meaning failures are real */

...do testing...


check_dmesg
unload


> +
> +# Test rootport disable/enable case
> +cycle_root_port() {
> +	load_kmod
> +	port=$("$CXL" list -b cxl_test -P | jq -r '.[0].port')
> +	[ -n "$port" ] || err "$LINENO"
> +
> +	"$CXL" disable-port "$port" -f
> +	region=$(cxl list -b cxl_test -R | jq -r '.[0].region // empty')

s/cxl/"$CXL"
s/cxl_test/"$CXL_TEST_BUS"
more of those need fixup below

> +	[ -z "$region" ] || err "$LINENO"
> +
> +	"$CXL" enable-port "$port"
> +	echo cxl_type2_accel.0 > /sys/bus/platform/drivers/cxl_mock_accel/bind
> +	region=$(cxl list -b cxl_test -R | jq -r '.[0].region')
> +	[ -n "$region" ] || err "$LINENO"
> +	check_dmesg "$LINENO"
> +	remove_kmod
> +}
> +
> +# Test reload firmware case

firmware

> +cycle_pdev_driver() {
> +	load_kmod
> +	region=$("$CXL" list -b cxl_test -R | jq -r '.[0].region')
> +	[ -n "$region" ] || err "$LINENO"
> +	echo cxl_type2_accel.0 > /sys/bus/platform/drivers/cxl_mock_accel/unbind
> +	region=$("$CXL" list -b cxl_test -R | jq -r '.[0].region // empty')
> +	[ -z "$region" ] || err "$LINENO"
> +	echo cxl_type2_accel.0 > /sys/bus/platform/drivers/cxl_mock_accel/bind
> +	region=$("$CXL" list -b cxl_test -R | jq -r '.[0].region')
> +	[ -n "$region" ] || err "$LINENO"
> +	check_dmesg "$LINENO"
> +	remove_kmod
> +}
> +
> +remove_kmod
> +rc=1
> +
> +init_check
> +cycle_root_port
> +cycle_pdev_driver
> diff --git a/test/meson.build b/test/meson.build
> index e0e2193bfd51..567347b655d2 100644
> --- a/test/meson.build
> +++ b/test/meson.build
> @@ -171,6 +171,7 @@ cxl_translate = find_program('cxl-translate.sh')
>  cxl_elc = find_program('cxl-elc.sh')
>  cxl_dax_hmem = find_program('cxl-dax-hmem.sh')
>  cxl_region_replay = find_program('cxl-region-replay.sh')
> +cxl_type2 = find_program('cxl-type2.sh')
>  
>  tests = [
>    [ 'libndctl',               libndctl,		  'ndctl' ],
> @@ -207,6 +208,7 @@ tests = [
>    [ 'cxl-elc.sh',             cxl_elc,            'cxl'   ],
>    [ 'cxl-dax-hmem.sh',        cxl_dax_hmem,       'cxl'   ],
>    [ 'cxl-region-replay.sh',   cxl_region_replay,  'cxl'   ],
> +  [ 'cxl-type2.sh',           cxl_type2,          'cxl'   ],
>  ]
>  
>  if get_option('destructive').enabled()
> 
> base-commit: 81c7cdd6cbcb4f1f77870ff02d8dd86298036f58
> -- 
> 2.53.0
>