From: Alison Schofield <alison.schofield@intel.com>
To: Davidlohr Bueso <dave@stgolabs.net>
Cc: <dave.jiang@intel.com>, <jic23@kernel.org>, <icheng@nvidia.com>,
<benjamin.cheatham@amd.com>, <alucerop@amd.com>,
<dongjoo.seo1@samsung.com>, <linux-cxl@vger.kernel.org>
Subject: Re: [PATCH v7 8/8] cxl: Allow auto-committed BI hdm decoders
Date: Tue, 4 Aug 2026 17:51:36 -0700 [thread overview]
Message-ID: <anKJGC7iXDifSHZt@aschofie-mobl2.lan> (raw)
In-Reply-To: <20260728144136.709882-9-dave@stgolabs.net>
On Tue, Jul 28, 2026 at 07:41:36AM -0700, Davidlohr Bueso wrote:
> Allow auto-committed BI hdm decoders on sane platforms, rejecting
> only broken paths (ie: one that cannot route BISnp, or BI paired
> with a host-only target range type).
>
> The respective region creation is done like any other committed
> decoder - with cxlds->bi set by the time an decoder attaches.
>
> A committed BI decoder under a window without the BI restriction is
> refused (undefined behavior per the CFMWS Window Restrictions), as
> is a committed decoder attaching to a region of a different
> coherency model.
Hi Davidlohr,
A question about reading the CTRL register twice -
>
> Signed-off-by: Davidlohr Bueso <dave@stgolabs.net>
> ---
> drivers/cxl/core/hdm.c | 24 +++++++++++++++++-------
> drivers/cxl/core/pci.c | 36 +++++++++++++++++++++++++++++-------
> drivers/cxl/core/region.c | 33 +++++++++++++++++++++++++++++++++
> drivers/cxl/port.c | 4 ++++
> 4 files changed, 83 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c
> index f437fe15c6df..c5be6fe4c77a 100644
> --- a/drivers/cxl/core/hdm.c
> +++ b/drivers/cxl/core/hdm.c
> @@ -1061,13 +1061,23 @@ static int init_hdm_decoder(struct cxl_port *port, struct cxl_decoder *cxld,
> else
> cxld->target_type = CXL_DECODER_DEVMEM;
>
> - /*
> - * Autocommit BI-enabled decoders is not supported.
> - * At this point cxlds->bi is not yet setup, so there
> - * are no guarantees that the platform supports BI.
> - */
> - if (FIELD_GET(CXL_HDM_DECODER0_CTRL_BI, ctrl))
> - return -ENXIO;
> + if (FIELD_GET(CXL_HDM_DECODER0_CTRL_BI, ctrl)) {
> + struct cxl_dev_state *cxlds = cxled ?
> + cxled_to_memdev(cxled)->cxlds : NULL;
Here we first read CTRL register -
> +
> + if (cxld->target_type == CXL_DECODER_HOSTONLYMEM) {
> + dev_warn(&port->dev,
> + "decoder%d.%d: BI with host-only\n",
> + port->id, cxld->id);
> + return -ENXIO;
> + }
> + if (cxlds && !cxlds->bi_capable) {
> + dev_warn(&port->dev,
> + "decoder%d.%d: path not BI capable\n",
> + port->id, cxld->id);
> + return -ENXIO;
> + }
> + }
>
> guard(rwsem_write)(&cxl_rwsem.region);
> if (cxld->id != cxl_num_decoders_committed(port)) {
>
> diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c
> index 76c6dc28a407..5578ef68034d 100644
> --- a/drivers/cxl/core/region.c
> +++ b/drivers/cxl/core/region.c
> @@ -1827,6 +1827,21 @@ static int cxl_region_attach_position(struct cxl_region *cxlr,
> return rc;
> }
>
> +/* Read back the committed BI bit of an auto-discovered decoder */
> +static bool cxled_committed_bi(struct cxl_endpoint_decoder *cxled)
> +{
> + struct cxl_port *port = cxled_to_port(cxled);
> + struct cxl_hdm *cxlhdm = dev_get_drvdata(&port->dev);
> + u32 ctrl;
> +
> + if (!cxlhdm || !cxlhdm->regs.hdm_decoder)
> + return false;
> +
> + ctrl = readl(cxlhdm->regs.hdm_decoder +
> + CXL_HDM_DECODER0_CTRL_OFFSET(cxled->cxld.id));
> + return FIELD_GET(CXL_HDM_DECODER0_CTRL_BI, ctrl);
And then we re-read it here. Could we record the bit at the earlier read?
> +}
snip to end
next prev parent reply other threads:[~2026-08-05 0:51 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-28 14:41 [PATCH v7 0/8] cxl: Support Back-Invalidate Davidlohr Bueso
2026-07-28 14:41 ` [PATCH v7 1/8] cxl: Add BI register probing and port initialization Davidlohr Bueso
2026-08-04 21:13 ` Dave Jiang
2026-08-05 0:42 ` Alison Schofield
2026-08-05 10:41 ` Li Ming
2026-08-07 5:38 ` Richard Cheng
2026-07-28 14:41 ` [PATCH v7 2/8] cxl/pci: Add BI topology enable/disable Davidlohr Bueso
2026-07-28 15:16 ` sashiko-bot
2026-08-03 18:55 ` Davidlohr Bueso
2026-08-05 12:49 ` Li Ming
2026-08-05 13:33 ` Li Ming
2026-08-07 6:54 ` Richard Cheng
2026-07-28 14:41 ` [PATCH v7 3/8] cxl/hdm: Add BI coherency support for endpoint decoders Davidlohr Bueso
2026-07-28 15:26 ` sashiko-bot
2026-07-28 18:44 ` Davidlohr Bueso
2026-07-28 14:41 ` [PATCH v7 4/8] cxl: Add HDM-DB region creation Davidlohr Bueso
2026-08-04 22:28 ` Dave Jiang
2026-08-05 0:11 ` Alison Schofield
2026-08-05 19:10 ` Davidlohr Bueso
2026-08-07 11:50 ` Richard Cheng
2026-07-28 14:41 ` [PATCH v7 5/8] cxl/hdm: Rename decoder coherency flags Davidlohr Bueso
2026-08-05 1:13 ` Alison Schofield
2026-07-28 14:41 ` [PATCH v7 6/8] cxl/region: Log the coherency model at region creation Davidlohr Bueso
2026-08-04 22:51 ` Dave Jiang
2026-07-28 14:41 ` [PATCH v7 7/8] cxl/pci: Split BI capability probe from setup Davidlohr Bueso
2026-08-04 23:07 ` Dave Jiang
2026-07-28 14:41 ` [PATCH v7 8/8] cxl: Allow auto-committed BI hdm decoders Davidlohr Bueso
2026-07-28 15:46 ` sashiko-bot
2026-08-03 19:04 ` Davidlohr Bueso
2026-08-04 23:22 ` Dave Jiang
2026-08-05 0:51 ` Alison Schofield [this message]
2026-08-05 20:53 ` Davidlohr Bueso
2026-08-07 12:03 ` Richard Cheng
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