Re: [PATCH v7 6/8] cxl/region: Log the coherency model at region creation

[Dave Jiang <dave.jiang@intel.com>]

On 7/28/26 7:41 AM, Davidlohr Bueso wrote:
> Region assembly emits plenty of debug information - resources,
> interleave geometry, target placement - but not the coherency model
> the region operates in.
> 
> Signed-off-by: Davidlohr Bueso <dave@stgolabs.net>

Reviewed-by: Dave Jiang <dave.jiang@intel.com>
> ---
>  drivers/cxl/core/region.c | 16 ++++++++++++++--
>  1 file changed, 14 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c
> index 840acc330ede..76c6dc28a407 100644
> --- a/drivers/cxl/core/region.c
> +++ b/drivers/cxl/core/region.c
> @@ -2741,6 +2741,17 @@ void kill_regions(struct cxl_root_decoder *cxlrd)
>  		unregister_region(cxlr);
>  }
>  
> +static const char *cxl_region_coherency(struct cxl_region *cxlr)
> +{
> +	if (cxlr->type == CXL_DECODER_HOSTONLYMEM)
> +		return "HDM-H";
> +
> +	if (cxl_root_decoder_is_bi(cxlr->cxlrd))
> +		return "HDM-DB";
> +
> +	return "HDM-D";
> +}
> +
>  /**
>   * devm_cxl_add_region - Adds a region to a decoder
>   * @cxlrd: root decoder
> @@ -2785,8 +2796,9 @@ static struct cxl_region *devm_cxl_add_region(struct cxl_root_decoder *cxlrd,
>  		return ERR_PTR(rc);
>  	}
>  
> -	dev_dbg(port->uport_dev, "%s: created %s\n",
> -		dev_name(&cxlrd->cxlsd.cxld.dev), dev_name(dev));
> +	dev_dbg(port->uport_dev, "%s: created %s %s\n",
> +		dev_name(&cxlrd->cxlsd.cxld.dev), cxl_region_coherency(cxlr),
> +		dev_name(dev));
>  	return cxlr;
>  err:
>  	put_device(dev);