From: Alison Schofield <alison.schofield@intel.com>
To: Srirangan Madhavan <smadhavan@nvidia.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>,
Dave Jiang <dave.jiang@intel.com>,
Davidlohr Bueso <dave@stgolabs.net>,
Ira Weiny <ira.weiny@intel.com>,
Jonathan Cameron <jic23@kernel.org>,
Vishal Verma <vishal.l.verma@intel.com>,
<linux-cxl@vger.kernel.org>, <linux-pci@vger.kernel.org>,
<linux-kernel@vger.kernel.org>,
Alex Williamson <alex.williamson@redhat.com>, <vsethi@nvidia.com>,
<alwilliamson@nvidia.com>,
Sai Yashwanth Reddy Kancherla <skancherla@nvidia.com>,
Vishal Aslot <vaslot@nvidia.com>,
Manish Honap <mhonap@nvidia.com>, Jiandi An <jan@nvidia.com>,
Richard Cheng <icheng@nvidia.com>, <linux-tegra@vger.kernel.org>
Subject: Re: [PATCH v15 16/16] tools/testing/cxl: Add HDM decoder range checks
Date: Mon, 26 Oct 2026 19:41:18 -0700 [thread overview]
Message-ID: <auAPTn-iZCFGqDfV@aschofie-mobl2.lan> (raw)
In-Reply-To: <20261011021422.3428136-17-smadhavan@nvidia.com>
On Sun, Oct 11, 2026 at 02:14:22AM +0000, Srirangan Madhavan wrote:
> Test cxl_hdm_unpack_decoder() when cxl_test loads, failing module loading
> if a check fails. Cover range boundaries and overflow, an all-ones base,
> zero-size and uncommitted decoders, and a locked host-only decoder with
> 12-way interleave. Verify the decoded fields for valid inputs.
>
> Run the checks separately from the watermark hooks, using a helper
> exported only by mock cxl_core. No PCI device or MMIO is needed.
Hi Srirangan,
Thanks for adding these tests. The boundary and overflow cases provide
valuable coverage for cxl_hdm_unpack_decoder().
However, the fact that these tests don't require the mock CXL topology
suggests that they belong in KUnit rather than cxl_test.
BTW, but pointless once this moves to KUNIT, as written a failure in
any one of these checks prevents the cxl_test module from loading,
meaning all cxl unit tests would skip or fail.
Please take a look at the recently posted CXL KUnit tests. I think
this would fit nicely there.
https://lore.kernel.org/all/cover.1791949910.git.alison.schofield@intel.com/
one bit inline below -
>
> Cache refresh, retained-state comparison, and reset restoration need
> follow-up tests with additional mock support. These checks do not cover
> reset sequencing or hardware cache invalidation.
>
> Signed-off-by: Srirangan Madhavan <smadhavan@nvidia.com>
> ---
> tools/testing/cxl/cxl_core_test.c | 78 +++++++++++++++++++++++++++++++
> tools/testing/cxl/cxl_core_test.h | 8 ++++
> tools/testing/cxl/test/cxl.c | 5 ++
> 3 files changed, 91 insertions(+)
> create mode 100644 tools/testing/cxl/cxl_core_test.h
>
> diff --git a/tools/testing/cxl/cxl_core_test.c b/tools/testing/cxl/cxl_core_test.c
> index 464a9255e4d6..8072146643bd 100644
> --- a/tools/testing/cxl/cxl_core_test.c
> +++ b/tools/testing/cxl/cxl_core_test.c
> @@ -1,6 +1,84 @@
> // SPDX-License-Identifier: GPL-2.0
> /* Copyright(c) 2022 Intel Corporation. All rights reserved. */
>
> +#include <linux/bitfield.h>
> +#include <linux/sizes.h>
> +#include "cxl.h"
> +#include "core.h"
> +#include "cxl_core_test.h"
> #include "watermark.h"
>
> cxl_test_watermark(cxl_core);
> +
> +/* Exercise the shared unpacker without HDM MMIO or a PCI device. */
> +int cxl_test_hdm_ranges(void)
> +{
> + static const struct {
> + const char *name;
> + u32 ctrl;
> + u64 base;
> + u64 size;
> + int rc;
> + unsigned long flags;
> + int ways;
> + int granularity;
> + enum cxl_decoder_type target_type;
> + } cases[] = {
> + { "valid", CXL_HDM_DECODER0_CTRL_COMMITTED,
> + SZ_1G, SZ_256M, 0, CXL_DECODER_F_ENABLE,
> + 1, 256, CXL_DECODER_DEVMEM },
> + { "overflow", CXL_HDM_DECODER0_CTRL_COMMITTED,
> + U64_MAX - 127, 256, -ENXIO },
> + { "all-ones base", CXL_HDM_DECODER0_CTRL_COMMITTED,
> + U64_MAX, SZ_256M, -ENXIO },
> + { "last address", CXL_HDM_DECODER0_CTRL_COMMITTED,
> + U64_MAX - 255, 256, 0, CXL_DECODER_F_ENABLE,
> + 1, 256, CXL_DECODER_DEVMEM },
> + { "zero size", CXL_HDM_DECODER0_CTRL_COMMITTED,
> + SZ_1G, 0, 0, CXL_DECODER_F_ENABLE,
> + 1, 256, CXL_DECODER_DEVMEM },
> + { "uncommitted stale size", 0,
> + SZ_1G, SZ_256M, 0, 0, 1, 256, 0 },
Above cases expects target___type 0 and IIUC that is not a valid
enum cxl_decoder_type value.
-- Alison
snip
prev parent reply other threads:[~2026-10-27 2:41 UTC|newest]
Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-11 2:14 [PATCH v15 00/16] PCI/CXL: Add CXL reset support for Type 2 devices Srirangan Madhavan
2026-10-11 2:14 ` [PATCH v15 01/16] cxl: Drop stale decoder interleave limit comment Srirangan Madhavan
2026-10-11 2:16 ` sashiko-bot
2026-10-27 4:13 ` Alison Schofield
2026-10-11 2:14 ` [PATCH v15 02/16] cxl: Share CXL port upstream PCI device lookup Srirangan Madhavan
2026-10-11 2:25 ` sashiko-bot
2026-10-11 2:14 ` [PATCH v15 03/16] cxl: Move decoder declarations to shared header Srirangan Madhavan
2026-10-11 2:19 ` sashiko-bot
2026-10-11 2:14 ` [PATCH v15 04/16] cxl: Embed decoder configuration in a standalone structure Srirangan Madhavan
2026-10-11 2:25 ` sashiko-bot
2026-10-11 2:14 ` [PATCH v15 05/16] cxl: Introduce endpoint HDM decoder settings Srirangan Madhavan
2026-10-11 2:22 ` sashiko-bot
2026-10-26 22:20 ` Dave Jiang
2026-10-27 6:23 ` Li Ming
2026-10-11 2:14 ` [PATCH v15 06/16] cxl: Move HDM decoder helpers to built-in code Srirangan Madhavan
2026-10-11 2:21 ` sashiko-bot
2026-10-26 22:32 ` Dave Jiang
2026-10-27 6:24 ` Li Ming
2026-10-11 2:14 ` [PATCH v15 07/16] cxl: Share HDM decoder register unpacking Srirangan Madhavan
2026-10-11 2:25 ` sashiko-bot
2026-10-26 22:41 ` Dave Jiang
2026-10-27 6:31 ` Li Ming
2026-10-11 2:14 ` [PATCH v15 08/16] cxl: Refresh cached PCI HDM decoder settings Srirangan Madhavan
2026-10-11 2:23 ` sashiko-bot
2026-10-26 22:56 ` Dave Jiang
2026-10-27 6:50 ` Li Ming
2026-10-11 2:14 ` [PATCH v15 09/16] PCI/CXL: Cache endpoint HDM state during PCI enumeration Srirangan Madhavan
2026-10-11 2:25 ` sashiko-bot
2026-10-27 8:07 ` Li Ming
2026-10-11 2:14 ` [PATCH v15 10/16] PCI/CXL: Add CXL Device Reset sequencing Srirangan Madhavan
2026-10-11 2:25 ` sashiko-bot
2026-10-28 3:01 ` Li Ming
2026-10-11 2:14 ` [PATCH v15 11/16] cxl: Validate and synchronize HDM ranges around reset Srirangan Madhavan
2026-10-11 2:21 ` sashiko-bot
2026-10-27 3:25 ` Alison Schofield
2026-10-27 4:32 ` Alison Schofield
2026-10-11 2:14 ` [PATCH v15 12/16] PCI/CXL: Reject reset with unsafe function scope Srirangan Madhavan
2026-10-11 2:28 ` sashiko-bot
2026-10-11 2:14 ` [PATCH v15 13/16] PCI/CXL: Restore CXL state after PCI reset Srirangan Madhavan
2026-10-11 2:25 ` sashiko-bot
2026-10-27 3:56 ` Alison Schofield
2026-10-11 2:14 ` [PATCH v15 14/16] PCI/CXL: Expose CXL Reset as a PCI reset method Srirangan Madhavan
2026-10-11 2:34 ` sashiko-bot
2026-10-11 2:14 ` [PATCH v15 15/16] PCI/CXL: Restore CXL state after CXL bus reset Srirangan Madhavan
2026-10-11 2:24 ` sashiko-bot
2026-10-11 2:14 ` [PATCH v15 16/16] tools/testing/cxl: Add HDM decoder range checks Srirangan Madhavan
2026-10-11 2:22 ` sashiko-bot
2026-10-27 2:41 ` Alison Schofield [this message]
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