From: Terry Bowman <Terry.Bowman@amd.com>
To: Jonathan Cameron <Jonathan.Cameron@Huawei.com>,
Robert Richter <rrichter@amd.com>
Cc: Alison Schofield <alison.schofield@intel.com>,
Vishal Verma <vishal.l.verma@intel.com>,
Ira Weiny <ira.weiny@intel.com>,
Ben Widawsky <bwidawsk@kernel.org>,
Dan Williams <dan.j.williams@intel.com>,
Davidlohr Bueso <dave@stgolabs.net>,
Dave Jiang <dave.jiang@intel.com>,
linux-cxl@vger.kernel.org, linux-kernel@vger.kernel.org,
Bjorn Helgaas <bhelgaas@google.com>
Subject: Re: [PATCH v11 14/20] cxl/pci: Map RCH downstream AER registers for logging protocol errors
Date: Mon, 9 Oct 2023 09:56:41 -0500 [thread overview]
Message-ID: <b8dca5f4-533d-4a9c-a177-fbdf3ad7848a@amd.com> (raw)
In-Reply-To: <20231002155658.00004ac0@Huawei.com>
On 10/2/23 09:56, Jonathan Cameron wrote:
> On Wed, 27 Sep 2023 17:43:33 +0200
> Robert Richter <rrichter@amd.com> wrote:
>
>> From: Terry Bowman <terry.bowman@amd.com>
>>
>> The restricted CXL host (RCH) error handler will log protocol errors
>> using AER and RAS status registers. The AER and RAS registers need to
>> be virtually memory mapped before enabling interrupts. Create the
>> initializer function devm_cxl_setup_parent_dport() for this when the
>> endpoint is connected with the dport. The initialization sets up the
>> RCH RAS and AER mappings.
>>
>> Add 'struct cxl_regs' to 'struct cxl_dport' for saving a pointer to
>> the RCH downstream port's AER and RAS registers.
>>
>> Co-developed-by: Robert Richter <rrichter@amd.com>
>> Signed-off-by: Terry Bowman <terry.bowman@amd.com>
> As before. Co-dev just before SoB.
>
> https://elixir.bootlin.com/linux/latest/source/Documentation/process/submitting-patches.rst#L521
> This example looks like what you have here.
>
>> Signed-off-by: Robert Richter <rrichter@amd.com>
> Otherwise, LGTM
>
> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Yes, we will fix.
Regards,
Terry
next prev parent reply other threads:[~2023-10-09 14:56 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-27 15:43 [PATCH v11 00/20] cxl/pci: Add support for RCH RAS error handling Robert Richter
2023-09-27 15:43 ` [PATCH v11 01/20] cxl/port: Fix release of RCD endpoints Robert Richter
2023-10-02 14:14 ` Jonathan Cameron
2023-09-27 15:43 ` [PATCH v11 02/20] cxl/core/regs: Rename @dev to @host in struct cxl_register_map Robert Richter
2023-10-02 14:19 ` Jonathan Cameron
2023-09-27 15:43 ` [PATCH v11 03/20] cxl/port: Fix @host confusion in cxl_dport_setup_regs() Robert Richter
2023-10-02 14:32 ` Jonathan Cameron
2023-09-27 15:43 ` [PATCH v11 04/20] cxl/port: Rename @comp_map to @reg_map in struct cxl_register_map Robert Richter
2023-10-02 14:34 ` Jonathan Cameron
2023-10-09 14:27 ` Terry Bowman
2023-09-27 15:43 ` [PATCH v11 05/20] cxl/port: Pre-initialize component register mappings Robert Richter
2023-09-27 15:43 ` [PATCH v11 06/20] cxl/pci: Store the endpoint's Component Register mappings in struct cxl_dev_state Robert Richter
2023-09-27 15:43 ` [PATCH v11 07/20] cxl/hdm: Use stored Component Register mappings to map HDM decoder capability Robert Richter
2023-10-02 14:43 ` Jonathan Cameron
2023-10-09 14:35 ` Terry Bowman
2023-10-16 14:09 ` Robert Richter
2023-09-27 15:43 ` [PATCH v11 08/20] cxl/pci: Remove Component Register base address from struct cxl_dev_state Robert Richter
2023-09-27 15:43 ` [PATCH v11 09/20] cxl/port: Remove Component Register base address from struct cxl_port Robert Richter
2023-09-27 15:43 ` [PATCH v11 10/20] cxl/pci: Introduce config option PCIEAER_CXL Robert Richter
2023-10-02 14:46 ` Jonathan Cameron
2023-10-09 14:44 ` Terry Bowman
2023-10-16 13:40 ` Terry Bowman
2023-10-16 14:08 ` Jonathan Cameron
2023-09-27 15:43 ` [PATCH v11 11/20] cxl/pci: Add RCH downstream port AER register discovery Robert Richter
2023-10-02 14:53 ` Jonathan Cameron
2023-10-09 14:55 ` Terry Bowman
2023-09-27 15:43 ` [PATCH v11 12/20] PCI/AER: Refactor cper_print_aer() for use by CXL driver module Robert Richter
2023-09-27 15:43 ` [PATCH v11 13/20] cxl/pci: Update CXL error logging to use RAS register address Robert Richter
2023-09-27 15:43 ` [PATCH v11 14/20] cxl/pci: Map RCH downstream AER registers for logging protocol errors Robert Richter
2023-10-02 14:56 ` Jonathan Cameron
2023-10-09 14:56 ` Terry Bowman [this message]
2023-09-27 15:43 ` [PATCH v11 15/20] cxl/pci: Add RCH downstream port error logging Robert Richter
2023-09-27 15:43 ` [PATCH v11 16/20] cxl/pci: Disable root port interrupts in RCH mode Robert Richter
2023-09-27 15:43 ` [PATCH v11 17/20] PCI/AER: Forward RCH downstream port-detected errors to the CXL.mem dev handler Robert Richter
2023-09-27 15:43 ` [PATCH v11 18/20] PCI/AER: Unmask RCEC internal errors to enable RCH downstream port error handling Robert Richter
2023-09-27 15:43 ` [PATCH v11 19/20] cxl/core/regs: Rename phys_addr in cxl_map_component_regs() Robert Richter
2023-09-27 15:43 ` [PATCH v11 20/20] cxl/core/regs: Rework cxl_map_pmu_regs() to use map->dev for devm Robert Richter
2023-10-02 15:01 ` Jonathan Cameron
2023-09-27 16:04 ` [PATCH v11 00/20] cxl/pci: Add support for RCH RAS error handling Robert Richter
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