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From: Dave Jiang <dave.jiang@intel.com>
To: Alison Schofield <alison.schofield@intel.com>,
	Davidlohr Bueso <dave@stgolabs.net>,
	Jonathan Cameron <jonathan.cameron@huawei.com>,
	Vishal Verma <vishal.l.verma@intel.com>,
	Ira Weiny <ira.weiny@intel.com>,
	Dan Williams <dan.j.williams@intel.com>
Cc: linux-cxl@vger.kernel.org
Subject: Re: [PATCH v3 2/3] cxl/acpi: Make the XOR calculations available for testing
Date: Thu, 18 Sep 2025 15:57:56 -0700	[thread overview]
Message-ID: <bbdec504-c1b7-40d6-b879-d2460254bc56@intel.com> (raw)
In-Reply-To: <76808ea6eb83a33dad50abc9707a4cf972d822d3.1758150087.git.alison.schofield@intel.com>



On 9/17/25 5:10 PM, Alison Schofield wrote:
> In preparation for adding a test module that can exercise the address
> translation functions performed by the CXL Driver, refactor the XOR
> implementation like this:
> 
> - Extract the core calculation into a standalone helper function,
> - Export the new function for use by test module cxl_translate only,
> - Enhance the parameter validation since this new function will be
>   called from a test module with no guarantee of valid parameters,
> - Move the define of struct cxl_cxims_data to cxl.h so the test module
>   can build xormaps.
> 
> Signed-off-by: Alison Schofield <alison.schofield@intel.com>

Reviewed-by: Dave Jiang <dave.jiang@intel.com>
> ---
>  drivers/cxl/acpi.c | 41 ++++++++++++++++++++++++++++++-----------
>  drivers/cxl/cxl.h  | 13 +++++++++++++
>  2 files changed, 43 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/cxl/acpi.c b/drivers/cxl/acpi.c
> index d7a5539d07d4..f981dcec463c 100644
> --- a/drivers/cxl/acpi.c
> +++ b/drivers/cxl/acpi.c
> @@ -11,25 +11,36 @@
>  #include "cxlpci.h"
>  #include "cxl.h"
>  
> -struct cxl_cxims_data {
> -	int nr_maps;
> -	u64 xormaps[] __counted_by(nr_maps);
> -};
> -
>  static const guid_t acpi_cxl_qtg_id_guid =
>  	GUID_INIT(0xF365F9A6, 0xA7DE, 0x4071,
>  		  0xA6, 0x6A, 0xB4, 0x0C, 0x0B, 0x4F, 0x8E, 0x52);
>  
> -static u64 cxl_apply_xor_maps(struct cxl_root_decoder *cxlrd, u64 addr)
> +#define HBIW_TO_NR_MAPS_SIZE (CXL_DECODER_MAX_INTERLEAVE + 1)
> +static const int hbiw_to_nr_maps[HBIW_TO_NR_MAPS_SIZE] = {
> +	[1] = 0, [2] = 1, [3] = 0, [4] = 2, [6] = 1, [8] = 3, [12] = 2, [16] = 4
> +};
> +
> +static const int valid_hbiw[] = { 1, 2, 3, 4, 6, 8, 12, 16 };
> +
> +u64 cxl_do_xormap_calc(struct cxl_cxims_data *cximsd, u64 addr, int hbiw)
>  {
> -	struct cxl_cxims_data *cximsd = cxlrd->platform_data;
> -	int hbiw = cxlrd->cxlsd.nr_targets;
> +	int nr_maps_to_apply = -1;
>  	u64 val;
>  	int pos;
>  
> -	/* No xormaps for host bridge interleave ways of 1 or 3 */
> -	if (hbiw == 1 || hbiw == 3)
> -		return addr;
> +	/*
> +	 * Strictly validate hbiw since this function is used for testing and
> +	 * that nullifies any expectation of trusted parameters from the CXL
> +	 * Region Driver.
> +	 */
> +	for (int i = 0; i < ARRAY_SIZE(valid_hbiw); i++) {
> +		if (valid_hbiw[i] == hbiw) {
> +			nr_maps_to_apply = hbiw_to_nr_maps[hbiw];
> +			break;
> +		}
> +	}
> +	if (nr_maps_to_apply == -1 || nr_maps_to_apply > cximsd->nr_maps)
> +		return ULLONG_MAX;
>  
>  	/*
>  	 * In regions using XOR interleave arithmetic the CXL HPA may not
> @@ -60,6 +71,14 @@ static u64 cxl_apply_xor_maps(struct cxl_root_decoder *cxlrd, u64 addr)
>  
>  	return addr;
>  }
> +EXPORT_SYMBOL_GPL_FOR_MODULES(cxl_do_xormap_calc, "cxl_translate");
> +
> +static u64 cxl_apply_xor_maps(struct cxl_root_decoder *cxlrd, u64 addr)
> +{
> +	struct cxl_cxims_data *cximsd = cxlrd->platform_data;
> +
> +	return cxl_do_xormap_calc(cximsd, addr, cxlrd->cxlsd.nr_targets);
> +}
>  
>  struct cxl_cxims_context {
>  	struct device *dev;
> diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
> index ee33fabfec4a..2b1f891049a2 100644
> --- a/drivers/cxl/cxl.h
> +++ b/drivers/cxl/cxl.h
> @@ -741,6 +741,19 @@ int cxl_validate_translation_params(u8 eiw, u16 eig, int pos);
>  u64 cxl_calculate_hpa_offset(u64 dpa_offset, int pos, u8 eiw, u16 eig);
>  u64 cxl_calculate_dpa_offset(u64 hpa_offset, u8 eiw, u16 eig);
>  int cxl_calculate_position(u64 hpa_offset, u8 eiw, u16 eig);
> +struct cxl_cxims_data {
> +	int nr_maps;
> +	u64 xormaps[] __counted_by(nr_maps);
> +};
> +
> +#if IS_ENABLED(CONFIG_CXL_ACPI)
> +u64 cxl_do_xormap_calc(struct cxl_cxims_data *cximsd, u64 addr, int hbiw);
> +#else
> +static inline u64 cxl_do_xormap_calc(struct cxl_cxims_data *cximsd, u64 addr, int hbiw)
> +{
> +	return ULLONG_MAX;
> +}
> +#endif
>  
>  int cxl_num_decoders_committed(struct cxl_port *port);
>  bool is_cxl_port(const struct device *dev);


  parent reply	other threads:[~2025-09-18 22:57 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-09-18  0:10 [PATCH v3 0/3] CXL: Add a loadable module for address translation Alison Schofield
2025-09-18  0:10 ` [PATCH v3 1/3] cxl/region: Refactor address translation funcs for testing Alison Schofield
2025-09-18 22:56   ` Dave Jiang
2025-09-18  0:10 ` [PATCH v3 2/3] cxl/acpi: Make the XOR calculations available " Alison Schofield
2025-09-18 15:32   ` Jonathan Cameron
2025-09-18 22:57   ` Dave Jiang [this message]
2025-09-18  0:10 ` [PATCH v3 3/3] cxl/test: Add cxl_translate module for address translation testing Alison Schofield

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