From: Li Ming <ming.li@zohomail.com>
To: Davidlohr Bueso <dave@stgolabs.net>, dave.jiang@intel.com
Cc: jic23@kernel.org, alison.schofield@intel.com, icheng@nvidia.com,
benjamin.cheatham@amd.com, alucerop@amd.com,
linux-cxl@vger.kernel.org,
Jonathan Cameron <jonathan.cameron@oss.qualcomm.com>
Subject: Re: [PATCH v9 05/10] cxl/hdm: Rename decoder coherency flags
Date: Thu, 24 Sep 2026 08:49:00 +0800 [thread overview]
Message-ID: <fa9d5743-e60b-4086-b46d-22652ccf284e@zohomail.com> (raw)
In-Reply-To: <3586f226c41a1b49e798d1f36b77ea54e573fc87.1790103847.git.dave@stgolabs.net>
On 9/23/2026 7:38 AM, Davidlohr Bueso wrote:
> Align with the ACPI CXL Window restriction naming and convert
> CXL_DECODER_F_TYPE2/F_TYPE3 to F_DEVMEM/F_HOSTONLY. Type2 and
> Type3 coherency models were named prior to Back-Invalidate.
>
> Reviewed-by: Ben Cheatham <benjamin.cheatham@amd.com>
> Reviewed-by: Dave Jiang <dave.jiang@intel.com>
> Reviewed-by: Alison Schofield <alison.schofield@intel.com>
> Reviewed-by: Jonathan Cameron <jonathan.cameron@oss.qualcomm.com>
> Signed-off-by: Davidlohr Bueso <dave@stgolabs.net>
Reviewed-by: Li Ming <ming.li@zohomail.com>
> ---
> drivers/cxl/acpi.c | 8 ++++----
> drivers/cxl/core/port.c | 12 ++++++------
> drivers/cxl/cxl.h | 4 ++--
> 3 files changed, 12 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/cxl/acpi.c b/drivers/cxl/acpi.c
> index 2e8e31544a5f..f04ac5275af8 100644
> --- a/drivers/cxl/acpi.c
> +++ b/drivers/cxl/acpi.c
> @@ -143,9 +143,9 @@ static unsigned long cfmws_to_decoder_flags(int restrictions)
> unsigned long flags = CXL_DECODER_F_ENABLE;
>
> if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_DEVMEM)
> - flags |= CXL_DECODER_F_TYPE2;
> + flags |= CXL_DECODER_F_DEVMEM;
> if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_HOSTONLYMEM)
> - flags |= CXL_DECODER_F_TYPE3;
> + flags |= CXL_DECODER_F_HOSTONLY;
> if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_VOLATILE)
> flags |= CXL_DECODER_F_RAM;
> if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_PMEM)
> @@ -459,8 +459,8 @@ static int __cxl_parse_cfmws(struct acpi_cedt_cfmws *cfmws,
> cxld->flags = cfmws_to_decoder_flags(cfmws->restrictions);
> /* host-only wins if firmware sets both coherency restrictions */
> cxld->target_type = CXL_DECODER_HOSTONLYMEM;
> - if (cxld->flags & CXL_DECODER_F_TYPE2) {
> - if (cxld->flags & CXL_DECODER_F_TYPE3)
> + if (cxld->flags & CXL_DECODER_F_DEVMEM) {
> + if (cxld->flags & CXL_DECODER_F_HOSTONLY)
> dev_dbg(dev, "CFMWS has both HDM-H and HDM-D\n");
> else
> cxld->target_type = CXL_DECODER_DEVMEM;
> diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
> index 1d26cd7c88a1..fa1574b46b6f 100644
> --- a/drivers/cxl/core/port.c
> +++ b/drivers/cxl/core/port.c
> @@ -129,8 +129,8 @@ static DEVICE_ATTR_RO(name)
>
> CXL_DECODER_FLAG_ATTR(cap_pmem, CXL_DECODER_F_PMEM);
> CXL_DECODER_FLAG_ATTR(cap_ram, CXL_DECODER_F_RAM);
> -CXL_DECODER_FLAG_ATTR(cap_type2, CXL_DECODER_F_TYPE2);
> -CXL_DECODER_FLAG_ATTR(cap_type3, CXL_DECODER_F_TYPE3);
> +CXL_DECODER_FLAG_ATTR(cap_type2, CXL_DECODER_F_DEVMEM);
> +CXL_DECODER_FLAG_ATTR(cap_type3, CXL_DECODER_F_HOSTONLY);
> CXL_DECODER_FLAG_ATTR(locked, CXL_DECODER_F_LOCK);
> CXL_DECODER_FLAG_ATTR(cap_back_invalidate, CXL_DECODER_F_BI);
>
> @@ -365,8 +365,8 @@ static bool can_create_pmem(struct cxl_root_decoder *cxlrd)
> unsigned long flags = cxlrd->cxlsd.cxld.flags;
> unsigned long hdm_h, hdm_db;
>
> - hdm_h = CXL_DECODER_F_TYPE3 | CXL_DECODER_F_PMEM;
> - hdm_db = CXL_DECODER_F_TYPE2 | CXL_DECODER_F_BI | CXL_DECODER_F_PMEM;
> + hdm_h = CXL_DECODER_F_HOSTONLY | CXL_DECODER_F_PMEM;
> + hdm_db = CXL_DECODER_F_DEVMEM | CXL_DECODER_F_BI | CXL_DECODER_F_PMEM;
>
> return (flags & hdm_h) == hdm_h || (flags & hdm_db) == hdm_db;
> }
> @@ -376,8 +376,8 @@ static bool can_create_ram(struct cxl_root_decoder *cxlrd)
> unsigned long flags = cxlrd->cxlsd.cxld.flags;
> unsigned long hdm_h, hdm_db;
>
> - hdm_h = CXL_DECODER_F_TYPE3 | CXL_DECODER_F_RAM;
> - hdm_db = CXL_DECODER_F_TYPE2 | CXL_DECODER_F_BI | CXL_DECODER_F_RAM;
> + hdm_h = CXL_DECODER_F_HOSTONLY | CXL_DECODER_F_RAM;
> + hdm_db = CXL_DECODER_F_DEVMEM | CXL_DECODER_F_BI | CXL_DECODER_F_RAM;
>
> return (flags & hdm_h) == hdm_h || (flags & hdm_db) == hdm_db;
> }
> diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
> index 9fb0278e2ce4..3639cd2daf0c 100644
> --- a/drivers/cxl/cxl.h
> +++ b/drivers/cxl/cxl.h
> @@ -296,8 +296,8 @@ int cxl_dport_map_rcd_linkcap(struct pci_dev *pdev, struct cxl_dport *dport);
> */
> #define CXL_DECODER_F_RAM BIT(0)
> #define CXL_DECODER_F_PMEM BIT(1)
> -#define CXL_DECODER_F_TYPE2 BIT(2)
> -#define CXL_DECODER_F_TYPE3 BIT(3)
> +#define CXL_DECODER_F_DEVMEM BIT(2)
> +#define CXL_DECODER_F_HOSTONLY BIT(3)
> #define CXL_DECODER_F_LOCK BIT(4)
> #define CXL_DECODER_F_ENABLE BIT(5)
> #define CXL_DECODER_F_NORMALIZED_ADDRESSING BIT(6)
next prev parent reply other threads:[~2026-09-24 0:49 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-22 23:38 [PATCH v9 0/10] cxl: Support Back-Invalidate Davidlohr Bueso
2026-09-22 23:38 ` [PATCH v9 01/10] cxl: Add BI register probing and port initialization Davidlohr Bueso
2026-09-29 4:06 ` Richard Cheng
2026-09-22 23:38 ` [PATCH v9 02/10] cxl/pci: Add BI topology enable/disable Davidlohr Bueso
2026-09-23 1:12 ` sashiko-bot
2026-09-23 17:00 ` Davidlohr Bueso
2026-09-23 5:41 ` Li Ming
2026-09-25 23:32 ` Jonathan Cameron
2026-09-29 8:52 ` Richard Cheng
2026-09-30 23:01 ` Alison Schofield
2026-09-22 23:38 ` [PATCH v9 03/10] cxl/hdm: Add BI coherency support for endpoint decoders Davidlohr Bueso
2026-09-23 6:06 ` Li Ming
2026-09-30 23:11 ` Alison Schofield
2026-09-22 23:38 ` [PATCH v9 04/10] cxl: Add HDM-DB region creation Davidlohr Bueso
2026-10-01 3:28 ` Alison Schofield
2026-10-01 8:57 ` Davidlohr Bueso
2026-09-22 23:38 ` [PATCH v9 05/10] cxl/hdm: Rename decoder coherency flags Davidlohr Bueso
2026-09-24 0:49 ` Li Ming [this message]
2026-09-22 23:38 ` [PATCH v9 06/10] cxl/region: Log the coherency model at region creation Davidlohr Bueso
2026-09-24 0:49 ` Li Ming
2026-09-30 23:10 ` Alison Schofield
2026-09-22 23:38 ` [PATCH v9 07/10] cxl/pci: Split BI capability probe from setup Davidlohr Bueso
2026-09-24 0:49 ` Li Ming
2026-09-30 23:09 ` Alison Schofield
2026-09-22 23:38 ` [PATCH v9 08/10] cxl: Allow auto-committed BI hdm decoders Davidlohr Bueso
2026-10-01 3:49 ` Alison Schofield
2026-09-22 23:38 ` [PATCH v9 09/10] cxl/test: Add mock BI topology support Davidlohr Bueso
2026-09-23 1:11 ` sashiko-bot
2026-09-23 20:57 ` Davidlohr Bueso
2026-09-23 0:43 ` [PATCH v9 10/10] cxl/doc: Update maturity map with BI support Davidlohr Bueso
2026-09-24 0:50 ` Li Ming
2026-09-30 23:08 ` Alison Schofield
2026-09-30 16:47 ` [PATCH v9 0/10] cxl: Support Back-Invalidate Alison Schofield
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