Re: [PATCH v9 10/10] cxl/doc: Update maturity map with BI support

[Alison Schofield <alison.schofield@intel.com>]

On Tue, Sep 22, 2026 at 05:43:25PM -0700, Davidlohr Bueso wrote:
> Add the respective Back-Invalidate info to the maturity map document.

Looks like this actually updates BI and Type2 status, which is good, 
just not stated in the commit subject or message.

If you're reving anyways, please fix that up.

Reviewed-by: Alison Schofield <alison.schofield@intel.com>


> 
> Reviewed-by: Jonathan Cameron <jonathan.cameron@oss.qualcomm.com>
> Signed-off-by: Davidlohr Bueso <dave@stgolabs.net>
> ---
>  Documentation/driver-api/cxl/maturity-map.rst | 16 +++++++++++++++-
>  1 file changed, 15 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/driver-api/cxl/maturity-map.rst b/Documentation/driver-api/cxl/maturity-map.rst
> index 282c1102dd81..0b857476cb47 100644
> --- a/Documentation/driver-api/cxl/maturity-map.rst
> +++ b/Documentation/driver-api/cxl/maturity-map.rst
> @@ -63,6 +63,11 @@ in place, but there are several corner cases that are pending closure.
>  
>    * [0] Decoder target and granularity constraints
>  
> +* [1] :ref:`Back-Invalidate (HDM-DB) <back-invalidate>`
> +
> +  * [3] BI topology enable / disable (endpoint, DSP, USP route table, RP)
> +  * [2] Firmware-enabled path adoption
> +
>  * [2] Performance enumeration
>  
>    * [3] Endpoint CDAT
> @@ -166,7 +171,7 @@ Accelerator
>  -----------
>  
>  * [0] Accelerator memory enumeration HDM-D (CXL 1.1/2.0 Type-2)
> -* [0] Accelerator memory enumeration HDM-DB (CXL 3.0 Type-2)
> +* [1] Accelerator memory enumeration HDM-DB (CXL 3.0 Type-2)
>  * [0] CXL.cache 68b (CXL 2.0)
>  * [0] CXL.cache 256b Cache IDs (CXL 3.0)
>  
> @@ -192,6 +197,15 @@ Details
>    hiding some standard registers like PCIe Link Status / Capabilities in
>    the CXL RCRB (Root Complex Register Block).
>  
> +.. _back-invalidate:
> +
> +* **Back-Invalidate**: HDM-DB lets a device snoop the host over the
> +  CXL.mem BISnp channel instead of CXL.cache. The kernel enables BI on
> +  every port between a device and its root port, requires 256B Flit
> +  mode on the path, adopts paths firmware already enabled, and creates
> +  HDM-DB regions under CFMWS windows carrying the Back-Invalidate
> +  restriction for Type 3 and Type 2 devices alike.
> +
>  .. _background-commands:
>  
>  * **Background commands**: The CXL background command mechanism is
> -- 
> 2.39.5
>