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From: Srirangan Madhavan <smadhavan@nvidia.com>
To: Li Ming <ming.li@zohomail.com>,
	Alison Schofield <alison.schofield@intel.com>,
	Bjorn Helgaas <bhelgaas@google.com>,
	Dan Williams <djbw@kernel.org>, Dave Jiang <dave.jiang@intel.com>,
	Davidlohr Bueso <dave@stgolabs.net>,
	Ira Weiny <ira.weiny@intel.com>,
	Jonathan Cameron <jic23@kernel.org>,
	Vishal Verma <vishal.l.verma@intel.com>,
	linux-cxl@vger.kernel.org, linux-pci@vger.kernel.org,
	linux-kernel@vger.kernel.org
Cc: Alex Williamson <alex.williamson@redhat.com>,
	vsethi@nvidia.com, alwilliamson@nvidia.com,
	Sai Yashwanth Reddy Kancherla <skancherla@nvidia.com>,
	Vishal Aslot <vaslot@nvidia.com>,
	Manish Honap <mhonap@nvidia.com>, Jiandi An <jan@nvidia.com>,
	Richard Cheng <icheng@nvidia.com>,
	linux-tegra@vger.kernel.org
Subject: Re: [PATCH v11 05/12] cxl: Cache endpoint decoder settings during PCI enumeration
Date: Thu, 10 Sep 2026 00:17:47 -0700	[thread overview]
Message-ID: <fb128492-aaab-4db6-98db-55c082865204@nvidia.com> (raw)
In-Reply-To: <d1eddf2d-43db-449b-976a-d70227210061@zohomail.com>

On 9/9/26 7:21 PM, Li Ming wrote:
> External email: Use caution opening links or attachments
> 
> 
> 在 2026/9/10 08:07, Srirangan Madhavan 写道:
>> On 9/2/26 7:03 AM, Li Ming wrote:
>>>> +             return true;
>>>> +
>>>> +     pci_cxl_hdm_init(pdev);
>>>
>>> I forgot to ask a question in v10, sorry about that.
>>>
>>> I am wondering why calling pci_cxl_hdm_init() in
>>> cxl_pci_hdm_decoder_count_match() is needed. pci_bus_add_device()
>>> already does pci_cxl_hdm_init(), so if my understanding is correct,
>>> pdev->hdm is not NULL here, so this pci_cxl_hdm_init() here will not do
>>> anything except checking if pdev->hdm is NULL. I am not sure if I miss
>>> some cases for that.
>>
>> Hi Li Ming!
>> Your question is valid. pci_bus_add_device() is the normal
>> initialization path. The later call is a retry for cases where that
>> attempt did not publish pdev->hdm, for example because allocation or
>> MMIO mapping failed at that point.
>> If initialization succeeded earlier, the existing cache is detected
>> and the retry returns without rebuilding it. I clarified this behavior
>> in the v12 commit message.
>>
> Hi Srirangan,
> 
> 
> Thanks for your explaination.
> 
> I think removing this retry should be better if it is only used for the
> case that allocation or MMIO mapping failure during
> pci_bus_add_device(). Because these failures are not expected to happen
> often, and removing it can make pci_cxl_hdm_init() implementation
> simpler. If only pci_bus_add_device() calls pci_cxl_hdm_init(), you
> won't have to hold cxl_rwsem.dpa and check whether pdev->hdm is NULL in
> __pci_cxl_hdm_init(). Besides, hold cxl_rwsem.dpa lock in
> pci_cxl_hdm_release() is not needed, because the function is called in
> pci_release_dev() where is at the end of this pci device's lifecycle.
> 
> 
> Ming

Hi Ming!

In v12 I removed the retry from the CXL core path and kept 
pci_cxl_hdm_init() only in pci_bus_add_device().
-- 
Regards,
Srirangan

  reply	other threads:[~2026-09-10  7:17 UTC|newest]

Thread overview: 39+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-09-02  7:27 [PATCH v11 00/12] PCI/CXL: Add CXL reset support for Type 2 devices Srirangan Madhavan
2026-09-02  7:27 ` [PATCH v11 01/12] cxl: Move HDM decoder programming helpers Srirangan Madhavan
2026-09-02  8:00   ` sashiko-bot
2026-09-02  7:27 ` [PATCH v11 02/12] cxl: Make HDM commit helpers available to reset code Srirangan Madhavan
2026-09-02  7:37   ` sashiko-bot
2026-09-02  7:27 ` [PATCH v11 03/12] cxl: Share HDM decoder decode logic Srirangan Madhavan
2026-09-02  7:39   ` sashiko-bot
2026-09-02  7:27 ` [PATCH v11 04/12] cxl: Cache decoder settings on PCI devices Srirangan Madhavan
2026-09-02  7:40   ` sashiko-bot
2026-09-02  7:27 ` [PATCH v11 05/12] cxl: Cache endpoint decoder settings during PCI enumeration Srirangan Madhavan
2026-09-02  7:41   ` sashiko-bot
2026-09-02 14:03   ` Li Ming
2026-09-10  0:07     ` Srirangan Madhavan
2026-09-10  2:21       ` Li Ming
2026-09-10  7:17         ` Srirangan Madhavan [this message]
2026-09-02  7:27 ` [PATCH v11 06/12] cxl: Add CXL Device Reset helper Srirangan Madhavan
2026-09-02  7:35   ` sashiko-bot
2026-09-02  7:27 ` [PATCH v11 07/12] cxl: Validate HDM ranges before CXL reset Srirangan Madhavan
2026-09-02  7:42   ` sashiko-bot
2026-09-04  9:19   ` Richard Cheng
2026-09-10  0:10     ` Srirangan Madhavan
2026-09-02  7:28 ` [PATCH v11 08/12] PCI/CXL: Reject CXL Reset on multifunction devices Srirangan Madhavan
2026-09-02  7:39   ` sashiko-bot
2026-09-04  9:26   ` Richard Cheng
2026-09-10  0:15     ` Srirangan Madhavan
2026-09-02  7:28 ` [PATCH v11 09/12] cxl: Restore CXL HDM state after PCI reset Srirangan Madhavan
2026-09-02  7:45   ` sashiko-bot
2026-09-04  9:23   ` Richard Cheng
2026-09-10  0:18     ` Srirangan Madhavan
2026-09-02  7:28 ` [PATCH v11 10/12] PCI/CXL: Expose CXL Reset as a PCI reset method Srirangan Madhavan
2026-09-02  7:51   ` sashiko-bot
2026-09-02  7:28 ` [PATCH v11 11/12] Documentation/ABI: Document CXL Reset " Srirangan Madhavan
2026-09-02  7:40   ` sashiko-bot
2026-09-02  7:28 ` [PATCH v11 12/12] PCI/CXL: Restore HDM state after CXL bus reset Srirangan Madhavan
2026-09-02  7:54   ` sashiko-bot
2026-09-04  9:15 ` [PATCH v11 00/12] PCI/CXL: Add CXL reset support for Type 2 devices Richard Cheng
2026-09-10  0:56   ` Srirangan Madhavan
2026-09-09 21:13 ` Alex Williamson
2026-09-10  1:01   ` Srirangan Madhavan

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