From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
To: Shawn Guo <shengchao.guo@oss.qualcomm.com>,
Bartosz Golaszewski <brgl@kernel.org>
Cc: Bjorn Andersson <andersson@kernel.org>,
Linus Walleij <linusw@kernel.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
stable@vger.kernel.org
Subject: Re: [PATCH] pinctrl: qcom: nord: Split QUP1 SE2/SE3 into lane-pair functions
Date: Wed, 19 Aug 2026 17:27:34 +0200 [thread overview]
Message-ID: <000076bd-b3fd-42dc-bd43-96ee9492a638@oss.qualcomm.com> (raw)
In-Reply-To: <20260819152356.904023-1-shengchao.guo@oss.qualcomm.com>
On 8/19/26 5:23 PM, Shawn Guo wrote:
> QUP1 SE2 and SE3 pack all four of their lanes pair-wise onto only two
> pins each: lanes 0/1 (I2C SDA/SCL) at mux value 2 and lanes 2/3 (UART
> TX/RX) at mux value 1, on gpio127/gpio128 and gpio129/gpio130
> respectively.
[...]
> + msm_mux_qup1_se2_01,
other drivers where this is necessary stick an 'l' before the
lane indices, e.g. se2_l2, let's keep this
The bindings change must be separate
Konrad
next prev parent reply other threads:[~2026-08-19 15:27 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-19 15:23 [PATCH] pinctrl: qcom: nord: Split QUP1 SE2/SE3 into lane-pair functions Shawn Guo
2026-08-19 15:27 ` Konrad Dybcio [this message]
2026-08-20 1:15 ` Shawn Guo
2026-08-24 8:44 ` Konrad Dybcio
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