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From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
To: Qiang Yu <qiang.yu@oss.qualcomm.com>,
	Bjorn Andersson <andersson@kernel.org>,
	Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>,
	Brian Masney <bmasney@redhat.com>, Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Taniya Das <taniya.das@oss.qualcomm.com>,
	Konrad Dybcio <konradybcio@kernel.org>
Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	krishna.chundru@oss.qualcomm.com
Subject: Re: [PATCH v6 3/8] clk: qcom: Add generic clkref_en support
Date: Mon, 22 Jun 2026 14:13:22 +0200	[thread overview]
Message-ID: <032d6002-2205-431a-abc7-7c0a010c9897@oss.qualcomm.com> (raw)
In-Reply-To: <20260621-tcsr_qref_0622-v6-3-c939c22ded0c@oss.qualcomm.com>

On 6/22/26 7:11 AM, Qiang Yu wrote:
> Before XO refclk is distributed to PCIe/USB/eDP PHYs, it passes through
> a QREF block. QREF is powered by dedicated LDO rails, and the clkref_en
> register controls whether refclk is gated through to the PHY side.
> 
> These clkref controls are different from typical GCC branch clocks:
> - only a single enable bit is present, without branch-style config bits
> - regulators must be voted before enable and unvoted after disable
> 
> Model this as a dedicated clk_ref clock type with custom clk_ops instead
> of reusing struct clk_branch semantics.
> 
> Also provide a common registration/probe API so the same clkref model
> can be reused regardless of where clkref_en registers are placed, e.g.
> TCSR on glymur and TLMM on SM8750.
> 
> Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
> ---

[...]

> +	for (clk_idx = 0; clk_idx < num_clk_refs; clk_idx++) {
> +		clk_ref = &clk_refs[clk_idx];
> +		desc = &descs[clk_idx];
> +
> +		if (!desc->name)
> +			continue;

Carrying over from the previous discussion:

> // this allows "holes" in dt-bindings for $reasons
> if (!desc)
> 	continue;
> 
> // this makes sure the programmer did not omit something important
> // while not taking the entire system down
> if (WARN_ON(!desc->name)
> 	continue;
>
The NULL name check is intentional - the descriptor array is indexed by
clock ID, and mahua has fewer clocks than glymur, leaving holes at
certain indices. So this is expected at runtime. WARN_ON would be noise
log here.


->

Your worry is captured by nullchecking `desc` (i.e. descs[clk_idx])

because in the mahua case we've got (ephemeral indices)

tcsr_cc_mahua_clk_descs[] = {
	[0] = { foo },
	// [1] is unassigned - OK
	[2] = { bar },
};

while (!desc->name) checks for:

tcsr_cc_mahua_clk_descs[] = {
	[0] = { .name = "foo", .offset = 0x10 },
	// name is NULL by virtue of partial struct initialization
	[1] = { .offset = 0x20 },
};

however I overlooked that we actually just have a normal array of
structs.. if we turn it into a struct pointer array with assigmnents
like:

[TCSR_EDP_CLKREF_EN] = &(const struct qcom_clk_ref_desc) {
	.name = "foo",
	...
};

we can achieve that

Konrad

  parent reply	other threads:[~2026-06-22 12:13 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-06-22  5:11 [PATCH v6 0/8] clk: qcom: Add common clkref support and migrate Glymur and Mahua Qiang Yu
2026-06-22  5:11 ` [PATCH v6 1/8] dt-bindings: clock: qcom: Move glymur TCSR to own binding Qiang Yu
2026-06-22  5:18   ` sashiko-bot
2026-06-22  7:30     ` Krzysztof Kozlowski
2026-06-22  7:29   ` Krzysztof Kozlowski
2026-06-22  5:11 ` [PATCH v6 2/8] dt-bindings: clock: qcom,glymur-tcsr: Add mahua support Qiang Yu
2026-06-22  5:16   ` sashiko-bot
2026-06-22  7:32   ` Krzysztof Kozlowski
2026-06-22  9:51     ` Qiang Yu
2026-06-22  5:11 ` [PATCH v6 3/8] clk: qcom: Add generic clkref_en support Qiang Yu
2026-06-22  5:24   ` sashiko-bot
2026-06-22 12:13   ` Konrad Dybcio [this message]
2026-06-22 12:36     ` Qiang Yu
2026-06-22  5:11 ` [PATCH v6 4/8] clk: qcom: tcsrcc-glymur: Add regulator supplies and migrate to clk_ref helper Qiang Yu
2026-06-22  5:11 ` [PATCH v6 5/8] clk: qcom: tcsrcc-glymur: Add Mahua QREF regulator support Qiang Yu
2026-06-22  5:21   ` sashiko-bot
2026-06-22 11:35   ` Konrad Dybcio
2026-06-22 12:49     ` Qiang Yu
2026-06-22 13:03       ` Konrad Dybcio
2026-06-22  5:11 ` [PATCH v6 6/8] arm64: dts: qcom: glymur: Add QREF regulator supplies to TCSR Qiang Yu
2026-06-22  5:21   ` sashiko-bot
2026-06-22 12:16   ` Konrad Dybcio
2026-06-22 13:24     ` Qiang Yu
2026-06-22  5:11 ` [PATCH v6 7/8] arm64: dts: qcom: mahua: " Qiang Yu
2026-06-22  5:22   ` sashiko-bot
2026-06-22 12:18   ` Konrad Dybcio
2026-06-22 13:31     ` Qiang Yu
2026-06-22  5:11 ` [PATCH v6 8/8] arm64: dts: qcom: mahua: Switch pcie5_phy ref clock to RPMH_CXO_CLK Qiang Yu
2026-06-22 11:37   ` Konrad Dybcio
2026-06-22 13:34     ` Qiang Yu

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