From: Andrew Lunn <andrew@lunn.ch>
To: 李志 <lizhi2@eswincomputing.com>
Cc: andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@google.com,
kuba@kernel.org, pabeni@redhat.com, robh@kernel.org,
krzk+dt@kernel.org, conor+dt@kernel.org, netdev@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
mcoquelin.stm32@gmail.com, alexandre.torgue@foss.st.com,
rmk+kernel@armlinux.org.uk, maxime.chevallier@bootlin.com,
linux-stm32@st-md-mailman.stormreply.com,
linux-arm-kernel@lists.infradead.org, ningyu@eswincomputing.com,
linmin@eswincomputing.com, pinkesh.vaghela@einfochips.com,
pritesh.patel@einfochips.com, weishangjuan@eswincomputing.com
Subject: Re: Re: [PATCH net v1 1/2] dt-bindings: ethernet: eswin: refine delay model and HSP register description
Date: Fri, 15 May 2026 15:14:06 +0200 [thread overview]
Message-ID: <0581dba0-c500-4a21-935f-9324692fce78@lunn.ch> (raw)
In-Reply-To: <29bee81.8323.19e2a8bf746.Coremail.lizhi2@eswincomputing.com>
> This will help determine whether this change should remain in the net
> series or be moved to a follow-up net-next series.
net-next. It does not fix anything which is broken, and bothers
people.
Andrew
next prev parent reply other threads:[~2026-05-15 13:14 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-07 8:30 [PATCH net v1 0/2] net: stmmac: eic7700: fix delay calculation and initialization ordering lizhi2
2026-05-07 8:31 ` [PATCH net v1 1/2] dt-bindings: ethernet: eswin: refine delay model and HSP register description lizhi2
2026-05-07 12:29 ` Andrew Lunn
2026-05-08 5:47 ` 李志
2026-05-15 7:31 ` 李志
2026-05-15 13:14 ` Andrew Lunn [this message]
2026-05-07 17:24 ` Conor Dooley
2026-05-08 5:43 ` 李志
2026-05-08 14:55 ` Conor Dooley
2026-05-07 8:32 ` [PATCH net v1 2/2] net: stmmac: eic7700: fix delay step calculation and ensure safe register initialization lizhi2
2026-05-07 11:21 ` Maxime Chevallier
2026-05-08 6:25 ` 李志
2026-05-08 17:14 ` sashiko-bot
2026-05-09 5:28 ` 李志
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