* [PATCH 2/2] clk: qcom: gcc-qcs8300: Add support for TSCSS clocks and resets
2026-08-05 16:47 [PATCH 0/2] clk: qcom: gcc-qcs8300: Add support for TSCSS clocks Imran Shaik
2026-08-05 16:47 ` [PATCH 1/2] dt-bindings: clock: qcom,qcs8300-gcc: Add TSCSS clocks and resets Imran Shaik
@ 2026-08-05 16:47 ` Imran Shaik
2026-08-05 17:42 ` Taniya Das
1 sibling, 1 reply; 4+ messages in thread
From: Imran Shaik @ 2026-08-05 16:47 UTC (permalink / raw)
To: Bjorn Andersson, Michael Turquette, Stephen Boyd, Brian Masney,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: Ajit Pandey, Taniya Das, Jagadeesh Kona, linux-arm-msm, linux-clk,
devicetree, linux-kernel, Imran Shaik
Add the GCC TSCSS clocks and reset support required for the Timestamp
Counter Subsystem (TSCSS) functionality on Qualcomm QCS8300 SoC.
Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
---
drivers/clk/qcom/gcc-qcs8300.c | 103 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 103 insertions(+)
diff --git a/drivers/clk/qcom/gcc-qcs8300.c b/drivers/clk/qcom/gcc-qcs8300.c
index 31fd870b10f7aee14b390fecb9e44b8d8a11a77e..146b3b5dfead31ab508fe3df62a44b559026e750 100644
--- a/drivers/clk/qcom/gcc-qcs8300.c
+++ b/drivers/clk/qcom/gcc-qcs8300.c
@@ -42,6 +42,7 @@ enum {
P_GCC_GPLL0_OUT_MAIN,
P_GCC_GPLL1_OUT_MAIN,
P_GCC_GPLL4_OUT_MAIN,
+ P_GCC_GPLL5_OUT_MAIN,
P_GCC_GPLL7_OUT_MAIN,
P_GCC_GPLL9_OUT_MAIN,
P_PCIE_0_PIPE_CLK,
@@ -128,6 +129,23 @@ static struct clk_alpha_pll gcc_gpll4 = {
},
};
+static struct clk_alpha_pll gcc_gpll5 = {
+ .offset = 0x5000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
+ .clkr = {
+ .enable_reg = 0x4b028,
+ .enable_mask = BIT(5),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_gpll5",
+ .parent_data = &(const struct clk_parent_data) {
+ .index = DT_BI_TCXO,
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_fixed_lucid_evo_ops,
+ },
+ },
+};
+
static struct clk_alpha_pll gcc_gpll7 = {
.offset = 0x7000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
@@ -364,6 +382,22 @@ static const struct clk_parent_data gcc_parent_data_18[] = {
{ .index = DT_BI_TCXO },
};
+static const struct parent_map gcc_parent_map_19[] = {
+ { P_BI_TCXO, 0 },
+ { P_GCC_GPLL7_OUT_MAIN, 2 },
+ { P_GCC_GPLL5_OUT_MAIN, 3 },
+ { P_GCC_GPLL4_OUT_MAIN, 5 },
+ { P_GCC_GPLL0_OUT_EVEN, 6 },
+};
+
+static const struct clk_parent_data gcc_parent_data_19[] = {
+ { .index = DT_BI_TCXO },
+ { .hw = &gcc_gpll7.clkr.hw },
+ { .hw = &gcc_gpll5.clkr.hw },
+ { .hw = &gcc_gpll4.clkr.hw },
+ { .hw = &gcc_gpll0_out_even.clkr.hw },
+};
+
static struct clk_regmap_mux gcc_pcie_0_phy_aux_clk_src = {
.reg = 0xa9074,
.shift = 0,
@@ -1094,6 +1128,25 @@ static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = {
},
};
+static const struct freq_tbl ftbl_gcc_tscss_cntr_clk_src[] = {
+ F(15625000, P_GCC_GPLL7_OUT_MAIN, 16, 1, 4),
+ { }
+};
+
+static struct clk_rcg2 gcc_tscss_cntr_clk_src = {
+ .cmd_rcgr = 0x21008,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_19,
+ .freq_tbl = ftbl_gcc_tscss_cntr_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "gcc_tscss_cntr_clk_src",
+ .parent_data = gcc_parent_data_19,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_19),
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {
F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
@@ -2899,6 +2952,50 @@ static struct clk_branch gcc_sgmi_clkref_en = {
},
};
+static struct clk_branch gcc_tscss_ahb_clk = {
+ .halt_reg = 0x21024,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x21024,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_tscss_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_tscss_etu_clk = {
+ .halt_reg = 0x21020,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x21020,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_tscss_etu_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_tscss_global_cntr_clk = {
+ .halt_reg = 0x21004,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x21004,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_tscss_global_cntr_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_tscss_cntr_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
static struct clk_branch gcc_ufs_phy_ahb_clk = {
.halt_reg = 0x83020,
.halt_check = BRANCH_HALT_VOTED,
@@ -3360,6 +3457,7 @@ static struct clk_regmap *gcc_qcs8300_clocks[] = {
[GCC_GPLL0_OUT_EVEN] = &gcc_gpll0_out_even.clkr,
[GCC_GPLL1] = &gcc_gpll1.clkr,
[GCC_GPLL4] = &gcc_gpll4.clkr,
+ [GCC_GPLL5] = &gcc_gpll5.clkr,
[GCC_GPLL7] = &gcc_gpll7.clkr,
[GCC_GPLL9] = &gcc_gpll9.clkr,
[GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr,
@@ -3464,6 +3562,10 @@ static struct clk_regmap *gcc_qcs8300_clocks[] = {
[GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
[GCC_SDCC1_ICE_CORE_CLK_SRC] = &gcc_sdcc1_ice_core_clk_src.clkr,
[GCC_SGMI_CLKREF_EN] = &gcc_sgmi_clkref_en.clkr,
+ [GCC_TSCSS_AHB_CLK] = &gcc_tscss_ahb_clk.clkr,
+ [GCC_TSCSS_CNTR_CLK_SRC] = &gcc_tscss_cntr_clk_src.clkr,
+ [GCC_TSCSS_ETU_CLK] = &gcc_tscss_etu_clk.clkr,
+ [GCC_TSCSS_GLOBAL_CNTR_CLK] = &gcc_tscss_global_cntr_clk.clkr,
[GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
[GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
[GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
@@ -3523,6 +3625,7 @@ static const struct qcom_reset_map gcc_qcs8300_resets[] = {
[GCC_PCIE_1_PHY_BCR] = { 0xae08c },
[GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR] = { 0xae094 },
[GCC_SDCC1_BCR] = { 0x20000 },
+ [GCC_TSCSS_BCR] = { 0x21000 },
[GCC_UFS_PHY_BCR] = { 0x83000 },
[GCC_USB20_PRIM_BCR] = { 0x1c000 },
[GCC_USB2_PHY_PRIM_BCR] = { 0x5c01c },
--
2.34.1
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