[PATCH 0/2] clk: qcom: Add EMAC CNOC APB clocks for Nord SoC

[PATCH 0/2] clk: qcom: Add EMAC CNOC APB clocks for Nord SoC

[Taniya Das]

Add support for the EMAC0 and EMAC1 config NoC (CNOC) APB clocks in the
SE_GCC clock controller on the Qualcomm Nord SoC. These branch clocks
gate the config NoC APB access path to the two EMAC (Ethernet MAC)
controllers and must be enabled for register access to the Ethernet
MACs.

Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
---
Taniya Das (2):
      dt-bindings: clock: qcom: Add EMAC CNOC APB clocks for Nord
      clk: qcom: segcc-nord: Add EMAC CNOC APB clocks for Nord SoC

 drivers/clk/qcom/segcc-nord.c               | 32 +++++++++++++++++++++++++++++
 include/dt-bindings/clock/qcom,nord-segcc.h |  2 ++
 2 files changed, 34 insertions(+)
---
base-commit: 7079a12d7506b07fb53b54a664bfad5fa9b16d70
change-id: 20260821-nords_emac_apb_clk-81863e60d066

Best regards,
-- 
Taniya Das <taniya.das@oss.qualcomm.com>

[PATCH 1/2] dt-bindings: clock: qcom: Add EMAC CNOC APB clocks for Nord

[Taniya Das]

Add the EMAC0 and EMAC1 CNOC APB clock IDs to the SE_GCC clock
controller bindings for the Qualcomm Nord SoC.

Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
---
 include/dt-bindings/clock/qcom,nord-segcc.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/dt-bindings/clock/qcom,nord-segcc.h b/include/dt-bindings/clock/qcom,nord-segcc.h
index f0f7422af692d05417d126c1011a22faf3bdc611..de4539b999850294926854a45db2997043c74f2c 100644
--- a/include/dt-bindings/clock/qcom,nord-segcc.h
+++ b/include/dt-bindings/clock/qcom,nord-segcc.h
@@ -84,6 +84,8 @@
 #define SE_GCC_QUPV3_WRAP1_S6_CLK				74
 #define SE_GCC_QUPV3_WRAP1_S6_CLK_SRC				75
 #define SE_GCC_QUPV3_WRAP1_S_AHB_CLK				76
+#define SE_GCC_EMAC0_CNOC_APB_CLK				77
+#define SE_GCC_EMAC1_CNOC_APB_CLK				78
 
 /* SE_GCC power domains */
 #define SE_GCC_EMAC0_GDSC					0

-- 
2.34.1

Re: [PATCH 1/2] dt-bindings: clock: qcom: Add EMAC CNOC APB clocks for Nord

[Abel Vesa]

On 26-08-24 12:23:29, Taniya Das wrote:
> Add the EMAC0 and EMAC1 CNOC APB clock IDs to the SE_GCC clock
> controller bindings for the Qualcomm Nord SoC.
> 
> Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>

Fixes tag, maybe ?

Re: [PATCH 1/2] dt-bindings: clock: qcom: Add EMAC CNOC APB clocks for Nord

[Krzysztof Kozlowski]

On 24/08/2026 10:11, Abel Vesa wrote:
> On 26-08-24 12:23:29, Taniya Das wrote:
>> Add the EMAC0 and EMAC1 CNOC APB clock IDs to the SE_GCC clock
>> controller bindings for the Qualcomm Nord SoC.
>>
>> Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
> 
> Fixes tag, maybe ?

Then also describe the observable bug. Fixes tag should not be used if
there is no bug.

Best regards,
Krzysztof

Re: [PATCH 1/2] dt-bindings: clock: qcom: Add EMAC CNOC APB clocks for Nord

[Krzysztof Kozlowski]

On 24/08/2026 08:53, Taniya Das wrote:
> Add the EMAC0 and EMAC1 CNOC APB clock IDs to the SE_GCC clock
> controller bindings for the Qualcomm Nord SoC.
> 


Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>

Best regards,
Krzysztof

[PATCH 2/2] clk: qcom: segcc-nord: Add EMAC CNOC APB clocks for Nord SoC

[Taniya Das]

Add the EMAC0 and EMAC1 CNOC APB clocks to the SE_GCC clock controller
on the Qualcomm Nord SoC. These branch clocks gate the config NoC APB
access to the two EMAC controllers and are required for register access
to the Ethernet MACs.

Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
---
 drivers/clk/qcom/segcc-nord.c | 32 ++++++++++++++++++++++++++++++++
 1 file changed, 32 insertions(+)

diff --git a/drivers/clk/qcom/segcc-nord.c b/drivers/clk/qcom/segcc-nord.c
index 51d7f83e21b6b2f2780088f26f547cc48801c6e4..aa807980d464d90e6a1ae209612b0ba9841bb35d 100644
--- a/drivers/clk/qcom/segcc-nord.c
+++ b/drivers/clk/qcom/segcc-nord.c
@@ -747,6 +747,21 @@ static struct clk_branch se_gcc_emac0_cc_sgmiiphy_tx_clk = {
 	},
 };
 
+static struct clk_branch se_gcc_emac0_cnoc_apb_clk = {
+	.halt_reg = 0x24018,
+	.halt_check = BRANCH_HALT_VOTED,
+	.hwcg_reg = 0x24018,
+	.hwcg_bit = 1,
+	.clkr = {
+		.enable_reg = 0x24018,
+		.enable_mask = BIT(0),
+		.hw.init = &(const struct clk_init_data) {
+			.name = "se_gcc_emac0_cnoc_apb_clk",
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
 static struct clk_branch se_gcc_emac0_phy_aux_clk = {
 	.halt_reg = 0x2402c,
 	.halt_check = BRANCH_HALT,
@@ -894,6 +909,21 @@ static struct clk_branch se_gcc_emac1_cc_sgmiiphy_tx_clk = {
 	},
 };
 
+static struct clk_branch se_gcc_emac1_cnoc_apb_clk = {
+	.halt_reg = 0x25018,
+	.halt_check = BRANCH_HALT_VOTED,
+	.hwcg_reg = 0x25018,
+	.hwcg_bit = 1,
+	.clkr = {
+		.enable_reg = 0x25018,
+		.enable_mask = BIT(0),
+		.hw.init = &(const struct clk_init_data) {
+			.name = "se_gcc_emac1_cnoc_apb_clk",
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
 static struct clk_branch se_gcc_emac1_phy_aux_clk = {
 	.halt_reg = 0x2502c,
 	.halt_check = BRANCH_HALT,
@@ -1458,6 +1488,7 @@ static struct clk_regmap *se_gcc_nord_clocks[] = {
 	[SE_GCC_EMAC0_AXI_CLK] = &se_gcc_emac0_axi_clk.clkr,
 	[SE_GCC_EMAC0_CC_SGMIIPHY_RX_CLK] = &se_gcc_emac0_cc_sgmiiphy_rx_clk.clkr,
 	[SE_GCC_EMAC0_CC_SGMIIPHY_TX_CLK] = &se_gcc_emac0_cc_sgmiiphy_tx_clk.clkr,
+	[SE_GCC_EMAC0_CNOC_APB_CLK] = &se_gcc_emac0_cnoc_apb_clk.clkr,
 	[SE_GCC_EMAC0_PHY_AUX_CLK] = &se_gcc_emac0_phy_aux_clk.clkr,
 	[SE_GCC_EMAC0_PHY_AUX_CLK_SRC] = &se_gcc_emac0_phy_aux_clk_src.clkr,
 	[SE_GCC_EMAC0_PTP_CLK] = &se_gcc_emac0_ptp_clk.clkr,
@@ -1471,6 +1502,7 @@ static struct clk_regmap *se_gcc_nord_clocks[] = {
 	[SE_GCC_EMAC1_AXI_CLK] = &se_gcc_emac1_axi_clk.clkr,
 	[SE_GCC_EMAC1_CC_SGMIIPHY_RX_CLK] = &se_gcc_emac1_cc_sgmiiphy_rx_clk.clkr,
 	[SE_GCC_EMAC1_CC_SGMIIPHY_TX_CLK] = &se_gcc_emac1_cc_sgmiiphy_tx_clk.clkr,
+	[SE_GCC_EMAC1_CNOC_APB_CLK] = &se_gcc_emac1_cnoc_apb_clk.clkr,
 	[SE_GCC_EMAC1_PHY_AUX_CLK] = &se_gcc_emac1_phy_aux_clk.clkr,
 	[SE_GCC_EMAC1_PHY_AUX_CLK_SRC] = &se_gcc_emac1_phy_aux_clk_src.clkr,
 	[SE_GCC_EMAC1_PTP_CLK] = &se_gcc_emac1_ptp_clk.clkr,

-- 
2.34.1

Re: [PATCH 2/2] clk: qcom: segcc-nord: Add EMAC CNOC APB clocks for Nord SoC

[Abel Vesa]

On 26-08-24 12:23:30, Taniya Das wrote:
> Add the EMAC0 and EMAC1 CNOC APB clocks to the SE_GCC clock controller
> on the Qualcomm Nord SoC. These branch clocks gate the config NoC APB
> access to the two EMAC controllers and are required for register access
> to the Ethernet MACs.
> 
> Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>

Fixes tag, maybe?

Looks good otherwise, so:

Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>

Re: [PATCH 2/2] clk: qcom: segcc-nord: Add EMAC CNOC APB clocks for Nord SoC

[Krzysztof Kozlowski]

On 24/08/2026 10:12, Abel Vesa wrote:
> On 26-08-24 12:23:30, Taniya Das wrote:
>> Add the EMAC0 and EMAC1 CNOC APB clocks to the SE_GCC clock controller
>> on the Qualcomm Nord SoC. These branch clocks gate the config NoC APB
>> access to the two EMAC controllers and are required for register access
>> to the Ethernet MACs.
>>
>> Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
> 
> Fixes tag, maybe?

Same here. Fixes needs proper bug description.

Best regards,
Krzysztof

Re: [PATCH 2/2] clk: qcom: segcc-nord: Add EMAC CNOC APB clocks for Nord SoC

[Konrad Dybcio]

On 8/24/26 8:53 AM, Taniya Das wrote:
> Add the EMAC0 and EMAC1 CNOC APB clocks to the SE_GCC clock controller
> on the Qualcomm Nord SoC. These branch clocks gate the config NoC APB
> access to the two EMAC controllers and are required for register access
> to the Ethernet MACs.
> 
> Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
> ---

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad