[PATCH 1/2] dt/bindings/spi: Add bindings for PIC32 Quad-SPI driver.

[PATCH 1/2] dt/bindings/spi: Add bindings for PIC32 Quad-SPI driver.

[Purna Chandra Mandal]

Document Device tree bindings for quad SPI peripheral
found on Microchip PIC32 class devices.

Signed-off-by: Purna Chandra Mandal <purna.mandal-UWL1GkI3JZL3oGB3hsPCZA@public.gmane.org>

Cc: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Cc: Mark Brown <broonie-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
---

 Documentation/devicetree/bindings/spi/sqi-pic32.txt | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/spi/sqi-pic32.txt

diff --git a/Documentation/devicetree/bindings/spi/sqi-pic32.txt b/Documentation/devicetree/bindings/spi/sqi-pic32.txt
new file mode 100644
index 0000000..5af9fab
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/sqi-pic32.txt
@@ -0,0 +1,18 @@
+Microchip PIC32 Quad SPI controller
+-----------------------------------
+Required properties:
+- compatible: Should be "microchip,pic32mzda-sqi".
+- reg: Address and length of SQI controller register space.
+- interrupts: Should contain SQI interrupt.
+- clocks: Should contain phandle of two clocks in sequence, clock that drives
+          clock on SPI bus and clock that drives SQI controller.
+- clock-names: Should be "spi_ck" and "reg_ck" in order.
+
+Example:
+	sqi1: sqi@1f8e2000 {
+		compatible = "microchip,pic32mzda-sqi";
+		reg = <0x1f8e2000 0x200>;
+		clocks = <&rootclk REF2CLK>, <&rootclk PB5CLK>;
+		clock-names = "spi_ck", "reg_ck";
+		interrupts = <169 IRQ_TYPE_LEVEL_HIGH>;
+	};
-- 
1.8.3.1

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Re: [PATCH 1/2] dt/bindings/spi: Add bindings for PIC32 Quad-SPI driver.

[Mark Brown]

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On Wed, Apr 13, 2016 at 06:42:04PM +0530, Purna Chandra Mandal wrote:
> Document Device tree bindings for quad SPI peripheral
> found on Microchip PIC32 class devices.

Please submit patches using subject lines reflecting the style for the
subsystem.  This makes it easier for people to identify relevant
patches.

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Re: [PATCH 1/2] dt/bindings/spi: Add bindings for PIC32 Quad-SPI driver.

[Rob Herring]

On Wed, Apr 13, 2016 at 06:42:04PM +0530, Purna Chandra Mandal wrote:
> Document Device tree bindings for quad SPI peripheral
> found on Microchip PIC32 class devices.
> 
> Signed-off-by: Purna Chandra Mandal <purna.mandal-UWL1GkI3JZL3oGB3hsPCZA@public.gmane.org>
> 
> Cc: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> Cc: Mark Brown <broonie-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> ---
> 
>  Documentation/devicetree/bindings/spi/sqi-pic32.txt | 18 ++++++++++++++++++
>  1 file changed, 18 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/spi/sqi-pic32.txt

One nit below, otherwise:

Acked-by: Rob Herring <rob-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>

> 
> diff --git a/Documentation/devicetree/bindings/spi/sqi-pic32.txt b/Documentation/devicetree/bindings/spi/sqi-pic32.txt
> new file mode 100644
> index 0000000..5af9fab
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/spi/sqi-pic32.txt
> @@ -0,0 +1,18 @@
> +Microchip PIC32 Quad SPI controller
> +-----------------------------------
> +Required properties:
> +- compatible: Should be "microchip,pic32mzda-sqi".
> +- reg: Address and length of SQI controller register space.
> +- interrupts: Should contain SQI interrupt.
> +- clocks: Should contain phandle of two clocks in sequence, clock that drives
> +          clock on SPI bus and clock that drives SQI controller.
> +- clock-names: Should be "spi_ck" and "reg_ck" in order.
> +
> +Example:
> +	sqi1: sqi@1f8e2000 {

spi@...

> +		compatible = "microchip,pic32mzda-sqi";
> +		reg = <0x1f8e2000 0x200>;
> +		clocks = <&rootclk REF2CLK>, <&rootclk PB5CLK>;
> +		clock-names = "spi_ck", "reg_ck";
> +		interrupts = <169 IRQ_TYPE_LEVEL_HIGH>;
> +	};
> -- 
> 1.8.3.1
> 
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