[PATCH v2 0/2] arm64: dts: rockchip: Add Radxa ROCK 3C

[PATCH v2 0/2] arm64: dts: rockchip: Add Radxa ROCK 3C

[Chukun Pan]

Changes in v2:
  Collected Acked-by.
  Drop cd-gpios for sdhci.
  Add mmc-hs200-1_8v to eMMC.
  Correct the spi max frequency.
  Update model name and compatible.
  Update regulator according to the schematic.

Chukun Pan (2):
  dt-bindings: arm: rockchip: add Radxa ROCK 3C
  arm64: dts: rockchip: Add Radxa ROCK 3C

 .../devicetree/bindings/arm/rockchip.yaml     |   5 +
 arch/arm64/boot/dts/rockchip/Makefile         |   1 +
 .../boot/dts/rockchip/rk3566-rock-3c.dts      | 750 ++++++++++++++++++
 3 files changed, 756 insertions(+)
 create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-rock-3c.dts

-- 
2.25.1

[PATCH v2 1/2] dt-bindings: arm: rockchip: add Radxa ROCK 3C

[Chukun Pan]

The Radxa ROCK 3C is a similar board to the
Radxa ROCK 3A with the Rockchip RK3566 SoC.
Add devicetree binding documentation for it.

Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
---
 Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml
index 1bbbaf81134b..e04c213a0dee 100644
--- a/Documentation/devicetree/bindings/arm/rockchip.yaml
+++ b/Documentation/devicetree/bindings/arm/rockchip.yaml
@@ -799,6 +799,11 @@ properties:
           - const: radxa,rock3a
           - const: rockchip,rk3568
 
+      - description: Radxa ROCK 3C
+        items:
+          - const: radxa,rock-3c
+          - const: rockchip,rk3566
+
       - description: Radxa ROCK 5A
         items:
           - const: radxa,rock-5a
-- 
2.25.1

Re: [PATCH v2 1/2] dt-bindings: arm: rockchip: add Radxa ROCK 3C

[Krzysztof Kozlowski]

On 28/04/2024 14:36, Chukun Pan wrote:
> The Radxa ROCK 3C is a similar board to the
> Radxa ROCK 3A with the Rockchip RK3566 SoC.
> Add devicetree binding documentation for it.

For future:

Please wrap commit message according to Linux coding style / submission
process (neither too early nor over the limit):
https://elixir.bootlin.com/linux/v6.4-rc1/source/Documentation/process/submitting-patches.rst#L597

> 
> Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
> Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
> ---
>  Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml
> index 1bbbaf81134b..e04c213a0dee 100644
> --- a/Documentation/devicetree/bindings/arm/rockchip.yaml
> +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml
> @@ -799,6 +799,11 @@ properties:
>            - const: radxa,rock3a
>            - const: rockchip,rk3568
>  
> +      - description: Radxa ROCK 3C

There was some big renaming of these boards. I assume you are using
correct naming?

Best regards,
Krzysztof

Re: [PATCH v2 1/2] dt-bindings: arm: rockchip: add Radxa ROCK 3C

[Dragan Simic]

Hello Krzysztof,

On 2024-04-28 18:37, Krzysztof Kozlowski wrote:
> On 28/04/2024 14:36, Chukun Pan wrote:
>> diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml 
>> b/Documentation/devicetree/bindings/arm/rockchip.yaml
>> index 1bbbaf81134b..e04c213a0dee 100644
>> --- a/Documentation/devicetree/bindings/arm/rockchip.yaml
>> +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml
>> @@ -799,6 +799,11 @@ properties:
>>            - const: radxa,rock3a
>>            - const: rockchip,rk3568
>> 
>> +      - description: Radxa ROCK 3C
> 
> There was some big renaming of these boards. I assume you are using
> correct naming?

I can confirm that the naming above is fine.

Re: [PATCH v2 1/2] dt-bindings: arm: rockchip: add Radxa ROCK 3C

[Chukun Pan]

>> The Radxa ROCK 3C is a similar board to the
>> Radxa ROCK 3A with the Rockchip RK3566 SoC.
>> Add devicetree binding documentation for it.

> For future:
>
> Please wrap commit message according to Linux coding style / submission
> process (neither too early nor over the limit)

Should I compress these three lines into two?

> There was some big renaming of these boards. I assume you are using
> correct naming?

According to the link below, the model name is now correct:
https://lore.kernel.org/lkml/B26C732A4DCEA9B3+282b8775-601b-4d4a-a513-4924b7940076@radxa.com/

Thanks,
Chukun

-- 
2.25.1

[PATCH v2 2/2] arm64: dts: rockchip: Add Radxa ROCK 3C

[Chukun Pan]

The Radxa ROCK 3C is a development board with the
Rockchip RK3566 SoC. It has the following features:

- 1/2/4GB LPDDR4
- 1x HDMI Type A
- 1x PCIE 2.0 slot
- 1x FAN connector
- 3.5mm jack with mic
- 1GbE RTL8211F Ethernet
- 1x USB 3.0, 3x USB 2.0
- 40-pin expansion header
- MicroSD card/eMMC socket
- 16MB SPI NOR (gd25lq128d)
- AP6256 or AIC8800 WiFi/BT

Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
---
 arch/arm64/boot/dts/rockchip/Makefile         |   1 +
 .../boot/dts/rockchip/rk3566-rock-3c.dts      | 750 ++++++++++++++++++
 2 files changed, 751 insertions(+)
 create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-rock-3c.dts

diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
index f6fff3fa29f7..c544ff507d20 100644
--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
@@ -91,6 +91,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-a.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-b.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-radxa-cm3-io.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-roc-pc.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-rock-3c.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-blade.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-cm4.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-model-a.dtb
diff --git a/arch/arm64/boot/dts/rockchip/rk3566-rock-3c.dts b/arch/arm64/boot/dts/rockchip/rk3566-rock-3c.dts
new file mode 100644
index 000000000000..936e7a2cc474
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3566-rock-3c.dts
@@ -0,0 +1,750 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/soc/rockchip,vop2.h>
+#include "rk3566.dtsi"
+
+/ {
+	model = "Radxa ROCK 3C";
+	compatible = "radxa,rock-3c", "rockchip,rk3566";
+
+	aliases {
+		ethernet0 = &gmac1;
+		mmc0 = &sdhci;
+		mmc1 = &sdmmc0;
+		mmc2 = &sdmmc1;
+	};
+
+	chosen: chosen {
+		stdout-path = "serial2:1500000n8";
+	};
+
+	gmac1_clkin: external-gmac1-clock {
+		compatible = "fixed-clock";
+		clock-frequency = <125000000>;
+		clock-output-names = "gmac1_clkin";
+		#clock-cells = <0>;
+	};
+
+	hdmi-con {
+		compatible = "hdmi-connector";
+		type = "a";
+
+		port {
+			hdmi_con_in: endpoint {
+				remote-endpoint = <&hdmi_out_con>;
+			};
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led-0 {
+			gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
+			function = LED_FUNCTION_HEARTBEAT;
+			color = <LED_COLOR_ID_BLUE>;
+			linux,default-trigger = "heartbeat";
+			pinctrl-names = "default";
+			pinctrl-0 = <&user_led2>;
+		};
+	};
+
+	rk809-sound {
+		compatible = "simple-audio-card";
+		simple-audio-card,format = "i2s";
+		simple-audio-card,name = "Analog RK809";
+		simple-audio-card,mclk-fs = <256>;
+
+		simple-audio-card,cpu {
+			sound-dai = <&i2s1_8ch>;
+		};
+
+		simple-audio-card,codec {
+			sound-dai = <&rk809>;
+		};
+	};
+
+	sdio_pwrseq: sdio-pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		clocks = <&rk809 1>;
+		clock-names = "ext_clock";
+		pinctrl-names = "default";
+		pinctrl-0 = <&wifi_reg_on_h>;
+		post-power-on-delay-ms = <100>;
+		power-off-delay-us = <5000000>;
+		reset-gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_LOW>;
+	};
+
+	vcc5v_dcin: vcc5v-dcin-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v_dcin";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+	};
+
+	vcc3v3_pcie: vcc3v3-pcie-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pcie_pwr_en>;
+		regulator-name = "vcc3v3_pcie";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc3v3_sys>;
+	};
+
+	vcc3v3_sys: vcc3v3-sys-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vcc5v0_sys: vcc5v0-sys-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc5v_dcin>;
+	};
+
+	vcc5v0_usb30_host: vcc5v0-usb30-host-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_usb30_host_en>;
+		regulator-name = "vcc5v0_usb30_host";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vcc5v0_usb_otg: vcc5v0-usb-otg-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_usb_otg_en>;
+		regulator-name = "vcc5v0_usb_otg";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vcc_cam: vcc-cam-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc_cam_en>;
+		regulator-name = "vcc_cam";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc3v3_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	vcc_mipi: vcc-mipi-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc_mipi_en>;
+		regulator-name = "vcc_mipi";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc3v3_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+};
+
+&combphy1 {
+	status = "okay";
+};
+
+&combphy2 {
+	status = "okay";
+};
+
+&cpu0 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu1 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu2 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu3 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&gmac1 {
+	assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
+	assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&gmac1_clkin>;
+	clock_in_out = "input";
+	phy-handle = <&rgmii_phy1>;
+	phy-mode = "rgmii-id";
+	phy-supply = <&vcc_3v3>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&gmac1m1_miim
+		     &gmac1m1_tx_bus2
+		     &gmac1m1_rx_bus2
+		     &gmac1m1_rgmii_clk
+		     &gmac1m1_rgmii_bus
+		     &gmac1m1_clkinout>;
+	status = "okay";
+};
+
+&gpu {
+	mali-supply = <&vdd_gpu>;
+	status = "okay";
+};
+
+&hdmi {
+	avdd-0v9-supply = <&vdda0v9_image>;
+	avdd-1v8-supply = <&vcca1v8_image>;
+	status = "okay";
+};
+
+&hdmi_in {
+	hdmi_in_vp0: endpoint {
+		remote-endpoint = <&vp0_out_hdmi>;
+	};
+};
+
+&hdmi_out {
+	hdmi_out_con: endpoint {
+		remote-endpoint = <&hdmi_con_in>;
+	};
+};
+
+&hdmi_sound {
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+
+	vdd_cpu: regulator@1c {
+		compatible = "tcs,tcs4525";
+		reg = <0x1c>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-name = "vdd_cpu";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <800000>;
+		regulator-max-microvolt = <1150000>;
+		regulator-ramp-delay = <2300>;
+		vin-supply = <&vcc5v0_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	rk809: pmic@20 {
+		compatible = "rockchip,rk809";
+		reg = <0x20>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
+		assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
+		assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
+		clock-output-names = "rk808-clkout1", "rk808-clkout2";
+		clock-names = "mclk";
+		clocks = <&cru I2S1_MCLKOUT_TX>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_int_l>, <&i2s1m0_mclk>;
+		system-power-controller;
+		vcc1-supply = <&vcc3v3_sys>;
+		vcc2-supply = <&vcc3v3_sys>;
+		vcc3-supply = <&vcc3v3_sys>;
+		vcc4-supply = <&vcc3v3_sys>;
+		vcc5-supply = <&vcc3v3_sys>;
+		vcc6-supply = <&vcc3v3_sys>;
+		vcc7-supply = <&vcc3v3_sys>;
+		vcc8-supply = <&vcc3v3_sys>;
+		vcc9-supply = <&vcc3v3_sys>;
+		wakeup-source;
+		#clock-cells = <1>;
+		#sound-dai-cells = <0>;
+
+		regulators {
+			vdd_logic: DCDC_REG1 {
+				regulator-name = "vdd_logic";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-initial-mode = <0x2>;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+					regulator-suspend-microvolt = <900000>;
+				};
+			};
+
+			vdd_gpu: DCDC_REG2 {
+				regulator-name = "vdd_gpu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-initial-mode = <0x2>;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+					regulator-suspend-microvolt = <900000>;
+				};
+			};
+
+			vcc_ddr: DCDC_REG3 {
+				regulator-name = "vcc_ddr";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-initial-mode = <0x2>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vdd_npu: DCDC_REG4 {
+				regulator-name = "vdd_npu";
+				regulator-initial-mode = <0x2>;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_1v8: DCDC_REG5 {
+				regulator-name = "vcc_1v8";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda0v9_image: LDO_REG1 {
+				regulator-name = "vdda0v9_image";
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda_0v9: LDO_REG2 {
+				regulator-name = "vdda_0v9";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda0v9_pmu: LDO_REG3 {
+				regulator-name = "vdda0v9_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <900000>;
+				};
+			};
+
+			vccio_acodec: LDO_REG4 {
+				regulator-name = "vccio_acodec";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vccio_sd: LDO_REG5 {
+				regulator-name = "vccio_sd";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_pmu: LDO_REG6 {
+				regulator-name = "vcc3v3_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vcca_1v8: LDO_REG7 {
+				regulator-name = "vcca_1v8";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcca1v8_pmu: LDO_REG8 {
+				regulator-name = "vcca1v8_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcca1v8_image: LDO_REG9 {
+				regulator-name = "vcca1v8_image";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_3v3: SWITCH_REG1 {
+				regulator-name = "vcc_3v3";
+				regulator-always-on;
+				regulator-boot-on;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_sd: SWITCH_REG2 {
+				regulator-name = "vcc3v3_sd";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+		};
+
+		codec {
+			mic-in-differential;
+		};
+	};
+
+	eeprom: eeprom@50 {
+		compatible = "belling,bl24c16a", "atmel,24c16";
+		reg = <0x50>;
+		pagesize = <16>;
+	};
+};
+
+&i2s0_8ch {
+	status = "okay";
+};
+
+&i2s1_8ch {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2s1m0_sclktx &i2s1m0_lrcktx &i2s1m0_sdi0 &i2s1m0_sdo0>;
+	rockchip,trcm-sync-tx-only;
+	status = "okay";
+};
+
+&mdio1 {
+	rgmii_phy1: ethernet-phy@1 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <0x1>;
+		reset-assert-us = <20000>;
+		reset-deassert-us = <100000>;
+		reset-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>;
+	};
+};
+
+&pcie2x1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie_reset_h>;
+	reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
+	vpcie3v3-supply = <&vcc3v3_pcie>;
+	status = "okay";
+};
+
+&pinctrl {
+	bluetooth {
+		bt_reg_on_h: bt-reg-on-h {
+			rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		bt_wake_host_h: bt-wake-host-h {
+			rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		bt_host_wake_h: bt-host-wake-h {
+			rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	cam {
+		vcc_cam_en: vcc_cam_en {
+			rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	display {
+		vcc_mipi_en: vcc_mipi_en {
+			rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	leds {
+		user_led2: user-led2 {
+			rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	pcie {
+		pcie_pwr_en: pcie-pwr-en {
+			rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		pcie_reset_h: pcie-reset-h {
+			rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	pmic {
+		pmic_int_l: pmic-int-l {
+			rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	usb {
+		vcc5v0_usb30_host_en: vcc5v0-usb30-host-en {
+			rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		vcc5v0_usb_otg_en: vcc5v0-usb-otg-en {
+			rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	wifi {
+		wifi_host_wake_h: wifi-host-wake-h {
+			rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		wifi_reg_on_h: wifi-reg-on-h {
+			rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+};
+
+&pmu_io_domains {
+	pmuio1-supply = <&vcc3v3_pmu>;
+	pmuio2-supply = <&vcca1v8_pmu>;
+	vccio1-supply = <&vccio_acodec>;
+	vccio2-supply = <&vcc_1v8>;
+	vccio3-supply = <&vccio_sd>;
+	vccio4-supply = <&vcca1v8_pmu>;
+	vccio5-supply = <&vcc_3v3>;
+	vccio6-supply = <&vcc_3v3>;
+	vccio7-supply = <&vcc_3v3>;
+	status = "okay";
+};
+
+&saradc {
+	vref-supply = <&vcca_1v8>;
+	status = "okay";
+};
+
+&sdhci {
+	bus-width = <8>;
+	max-frequency = <200000000>;
+	mmc-hs200-1_8v;
+	non-removable;
+	pinctrl-names = "default";
+	pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
+	vmmc-supply = <&vcc_3v3>;
+	vqmmc-supply = <&vcc_1v8>;
+	status = "okay";
+};
+
+&sdmmc0 {
+	bus-width = <4>;
+	cap-sd-highspeed;
+	disable-wp;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
+	sd-uhs-sdr50;
+	vmmc-supply = <&vcc3v3_sys>;
+	vqmmc-supply = <&vccio_sd>;
+	status = "okay";
+};
+
+&sdmmc1 {
+	bus-width = <4>;
+	cap-sd-highspeed;
+	cap-sdio-irq;
+	keep-power-in-suspend;
+	mmc-pwrseq = <&sdio_pwrseq>;
+	non-removable;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_clk &sdmmc1_cmd>;
+	sd-uhs-sdr104;
+	vmmc-supply = <&vcc3v3_sys>;
+	vqmmc-supply = <&vcca1v8_pmu>;
+	status = "okay";
+};
+
+&sfc {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "okay";
+
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0x0>;
+		spi-max-frequency = <120000000>;
+		spi-rx-bus-width = <4>;
+		spi-tx-bus-width = <1>;
+	};
+};
+
+&tsadc {
+	rockchip,hw-tshut-mode = <1>;
+	rockchip,hw-tshut-polarity = <0>;
+	status = "okay";
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart1m0_ctsn &uart1m0_rtsn &uart1m0_xfer>;
+	status = "okay";
+};
+
+&uart2 {
+	status = "okay";
+};
+
+&usb_host0_ehci {
+	status = "okay";
+};
+
+&usb_host0_ohci {
+	status = "okay";
+};
+
+&usb_host0_xhci {
+	dr_mode = "host";
+	status = "okay";
+};
+
+&usb_host1_ehci {
+	status = "okay";
+};
+
+&usb_host1_ohci {
+	status = "okay";
+};
+
+&usb_host1_xhci {
+	status = "okay";
+};
+
+&usb2phy0 {
+	status = "okay";
+};
+
+&usb2phy0_host {
+	phy-supply = <&vcc5v0_usb30_host>;
+	status = "okay";
+};
+
+&usb2phy0_otg {
+	phy-supply = <&vcc5v0_usb_otg>;
+	status = "okay";
+};
+
+&usb2phy1 {
+	status = "okay";
+};
+
+&usb2phy1_host {
+	phy-supply = <&vcc5v0_usb30_host>;
+	status = "okay";
+};
+
+&usb2phy1_otg {
+	phy-supply = <&vcc5v0_usb30_host>;
+	status = "okay";
+};
+
+&vop {
+	assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
+	assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
+	status = "okay";
+};
+
+&vop_mmu {
+	status = "okay";
+};
+
+&vp0 {
+	vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
+		reg = <ROCKCHIP_VOP2_EP_HDMI0>;
+		remote-endpoint = <&hdmi_in_vp0>;
+	};
+};
-- 
2.25.1

Re: [PATCH v2 2/2] arm64: dts: rockchip: Add Radxa ROCK 3C

[Folker Schwesinger]

On Sun Apr 28, 2024 at 2:36 PM CEST, Chukun Pan wrote:
> [...]
> +&sdhci {
> +	bus-width = <8>;
> +	max-frequency = <200000000>;
> +	mmc-hs200-1_8v;

Out of curiosity, does this board also support HS400? From a very brief
look this board seems quite similar to Rock 4 series boards, that do
support HS400.

> +	non-removable;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
> +	vmmc-supply = <&vcc_3v3>;
> +	vqmmc-supply = <&vcc_1v8>;
> +	status = "okay";
> +};

Re: [PATCH v2 2/2] arm64: dts: rockchip: Add Radxa ROCK 3C

[Dragan Simic]

Hello Folker,

On 2024-04-30 07:42, Folker Schwesinger wrote:
> On Sun Apr 28, 2024 at 2:36 PM CEST, Chukun Pan wrote:
>> [...]
>> +&sdhci {
>> +	bus-width = <8>;
>> +	max-frequency = <200000000>;
>> +	mmc-hs200-1_8v;
> 
> Out of curiosity, does this board also support HS400? From a very brief
> look this board seems quite similar to Rock 4 series boards, that do
> support HS400.

In a word, no, unfortunately.  In more detail, the Rockchip RK3566
and RK3568 SoCs support the eMMC modes up to and including HS200, but
not the HS400 mode.

>> +	non-removable;
>> +	pinctrl-names = "default";
>> +	pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
>> +	vmmc-supply = <&vcc_3v3>;
>> +	vqmmc-supply = <&vcc_1v8>;
>> +	status = "okay";
>> +};
> 
> 
> _______________________________________________
> Linux-rockchip mailing list
> Linux-rockchip@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-rockchip

Re: [PATCH v2 2/2] arm64: dts: rockchip: Add Radxa ROCK 3C

[Jonas Karlman]

Hi Dragan and Folker,

On 2024-05-02 03:28, Dragan Simic wrote:
> Hello Folker,
> 
> On 2024-04-30 07:42, Folker Schwesinger wrote:
>> On Sun Apr 28, 2024 at 2:36 PM CEST, Chukun Pan wrote:
>>> [...]
>>> +&sdhci {
>>> +	bus-width = <8>;
>>> +	max-frequency = <200000000>;
>>> +	mmc-hs200-1_8v;
>>
>> Out of curiosity, does this board also support HS400? From a very brief
>> look this board seems quite similar to Rock 4 series boards, that do
>> support HS400.
> 
> In a word, no, unfortunately.  In more detail, the Rockchip RK3566
> and RK3568 SoCs support the eMMC modes up to and including HS200, but
> not the HS400 mode.

The datasheet for RK3568 only mention HS200 mode, however, HS400 mode is
working in U-Boot after adjusting tap number for transmit clock [1].
Linux may need similar adjustment to make HS400 mode work on RK3568.

RK3566 that this board use only support HS200, as specified in datasheet.

[1] https://source.denx.de/u-boot/u-boot/-/commit/5c053f3adc69eaf83645b5d44c6adbb2d49a3fa7

Regards,
Jonas

> 
>>> +	non-removable;
>>> +	pinctrl-names = "default";
>>> +	pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
>>> +	vmmc-supply = <&vcc_3v3>;
>>> +	vqmmc-supply = <&vcc_1v8>;
>>> +	status = "okay";
>>> +};
>>

Re: [PATCH v2 2/2] arm64: dts: rockchip: Add Radxa ROCK 3C

[Dragan Simic]

Hello Jonas,

On 2024-05-02 14:17, Jonas Karlman wrote:
> On 2024-05-02 03:28, Dragan Simic wrote:
>> On 2024-04-30 07:42, Folker Schwesinger wrote:
>>> On Sun Apr 28, 2024 at 2:36 PM CEST, Chukun Pan wrote:
>>>> [...]
>>>> +&sdhci {
>>>> +	bus-width = <8>;
>>>> +	max-frequency = <200000000>;
>>>> +	mmc-hs200-1_8v;
>>> 
>>> Out of curiosity, does this board also support HS400? From a very 
>>> brief
>>> look this board seems quite similar to Rock 4 series boards, that do
>>> support HS400.
>> 
>> In a word, no, unfortunately.  In more detail, the Rockchip RK3566
>> and RK3568 SoCs support the eMMC modes up to and including HS200, but
>> not the HS400 mode.
> 
> The datasheet for RK3568 only mention HS200 mode, however, HS400 mode 
> is
> working in U-Boot after adjusting tap number for transmit clock [1].
> Linux may need similar adjustment to make HS400 mode work on RK3568.
> 
> RK3566 that this board use only support HS200, as specified in 
> datasheet.

Oh, that's very interesting, thanks for pointing it out!

What makes me a bit worried about enabling the undocumented HS400 mode
on the RK3568 is that neither the RK3568 Hardware Design Guide (HDG),
version 1.2, [2] mentions HS400 support.  I mean, the RK3568 datasheet
may be wrong about not mentioning HS400, but what are the chances for
the RK3568 HDG to also be wrong there?

In other words, maybe there are some hard-to-trigger hardware issues
in the RK3568 that made the HS400 mode, although actually present in
hardware, officially unsupported for the RK3568?  Maybe there's even
some non-public errata from Rockchip, who knows.

[1] 
https://source.denx.de/u-boot/u-boot/-/commit/5c053f3adc69eaf83645b5d44c6adbb2d49a3fa7
[2] https://dl.xkwy2018.com/downloads/RK3568/RK356X/Hardware/

Re: [PATCH v2 2/2] arm64: dts: rockchip: Add Radxa ROCK 3C

[Folker Schwesinger]

Hi Jonas and Dragan,

On Thu May 2, 2024 at 3:48 PM CEST, Dragan Simic wrote:
> >>>> [...]
> >>>> +&sdhci {
> >>>> +	bus-width = <8>;
> >>>> +	max-frequency = <200000000>;
> >>>> +	mmc-hs200-1_8v;
> >>> 
> >>> Out of curiosity, does this board also support HS400? From a very 
> >>> brief
> >>> look this board seems quite similar to Rock 4 series boards, that do
> >>> support HS400.
> >> 
> >> In a word, no, unfortunately.  In more detail, the Rockchip RK3566
> >> and RK3568 SoCs support the eMMC modes up to and including HS200, but
> >> not the HS400 mode.
> > 
> > The datasheet for RK3568 only mention HS200 mode, however, HS400 mode 
> > is
> > working in U-Boot after adjusting tap number for transmit clock [1].
> > Linux may need similar adjustment to make HS400 mode work on RK3568.
> > 
> > RK3566 that this board use only support HS200, as specified in 
> > datasheet.
>
> Oh, that's very interesting, thanks for pointing it out!
>
> What makes me a bit worried about enabling the undocumented HS400 mode
> on the RK3568 is that neither the RK3568 Hardware Design Guide (HDG),
> version 1.2, [2] mentions HS400 support.  I mean, the RK3568 datasheet
> may be wrong about not mentioning HS400, but what are the chances for
> the RK3568 HDG to also be wrong there?
>
> In other words, maybe there are some hard-to-trigger hardware issues
> in the RK3568 that made the HS400 mode, although actually present in
> hardware, officially unsupported for the RK3568?  Maybe there's even
> some non-public errata from Rockchip, who knows.
>
> [1] 
> https://source.denx.de/u-boot/u-boot/-/commit/5c053f3adc69eaf83645b5d44c6adbb2d49a3fa7
> [2] https://dl.xkwy2018.com/downloads/RK3568/RK356X/Hardware/

Interesting indeed! Thanks to both of you for the info and for providing
links to the U-Boot commit and design guide. Much appreciated!

Re: [PATCH v2 2/2] arm64: dts: rockchip: Add Radxa ROCK 3C

[Jonas Karlman]

Hi Chukun,

On 2024-04-28 14:36, Chukun Pan wrote:
> The Radxa ROCK 3C is a development board with the
> Rockchip RK3566 SoC. It has the following features:
> 
> - 1/2/4GB LPDDR4
> - 1x HDMI Type A
> - 1x PCIE 2.0 slot
> - 1x FAN connector
> - 3.5mm jack with mic
> - 1GbE RTL8211F Ethernet
> - 1x USB 3.0, 3x USB 2.0
> - 40-pin expansion header
> - MicroSD card/eMMC socket
> - 16MB SPI NOR (gd25lq128d)
> - AP6256 or AIC8800 WiFi/BT
> 
> Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
> ---
>  arch/arm64/boot/dts/rockchip/Makefile         |   1 +
>  .../boot/dts/rockchip/rk3566-rock-3c.dts      | 750 ++++++++++++++++++
>  2 files changed, 751 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-rock-3c.dts
> 

[snip]

> +
> +&i2c0 {
> +	status = "okay";
> +
> +	vdd_cpu: regulator@1c {
> +		compatible = "tcs,tcs4525";
> +		reg = <0x1c>;
> +		fcs,suspend-voltage-selector = <1>;
> +		regulator-name = "vdd_cpu";
> +		regulator-always-on;
> +		regulator-boot-on;
> +		regulator-min-microvolt = <800000>;
> +		regulator-max-microvolt = <1150000>;
> +		regulator-ramp-delay = <2300>;
> +		vin-supply = <&vcc5v0_sys>;
> +
> +		regulator-state-mem {
> +			regulator-off-in-suspend;
> +		};
> +	};
> +
> +	rk809: pmic@20 {
> +		compatible = "rockchip,rk809";
> +		reg = <0x20>;

[snip]

> +		codec {
> +			mic-in-differential;

This should be rockchip,mic-in-differential or removed.

> +		};
> +	};
> +
> +	eeprom: eeprom@50 {
> +		compatible = "belling,bl24c16a", "atmel,24c16";
> +		reg = <0x50>;
> +		pagesize = <16>;
> +	};
> +};
> +

[snip]

> +
> +&sdmmc0 {
> +	bus-width = <4>;
> +	cap-sd-highspeed;
> +	disable-wp;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
> +	sd-uhs-sdr50;

Do you have any references to issues related to why sd-uhs-sdr104 is not
used here?

My testing shows that io-domain is getting notified and correctly
configured during boot. And card seem to be working correctly.

[    2.162780] mmc_host mmc1: Bus speed (slot 0) = 375000Hz (slot req 400000Hz, actual 375000HZ div = 0)

[    2.229408] rockchip-iodomain fdc20000.syscon:io-domains: Setting to 3300000
[    2.230042] rockchip-iodomain fdc20000.syscon:io-domains: Setting to 3300000 done
[    2.231493] rockchip-iodomain fdc20000.syscon:io-domains: Setting to 1800000
[    2.232121] rockchip-iodomain fdc20000.syscon:io-domains: Setting to 1800000 done
[    2.257294] mmc_host mmc1: Bus speed (slot 0) = 150000000Hz (slot req 150000000Hz, actual 150000000HZ div = 0)
[    2.269482] dwmmc_rockchip fe2b0000.mmc: Successfully tuned phase to 254
[    2.270098] mmc1: new ultra high speed SDR104 SDXC card at address aaaa
[    2.271533] mmcblk1: mmc1:aaaa SD64G 59.5 GiB
[    2.277357]  mmcblk1: p1

Also when the card is later removed/re-inserted:

[   80.181598] mmc1: card aaaa removed
[   83.836785] rockchip-iodomain fdc20000.syscon:io-domains: Setting to 3300000
[   83.837611] rockchip-iodomain fdc20000.syscon:io-domains: Setting to 3300000 done
[   83.839263] rockchip-iodomain fdc20000.syscon:io-domains: Setting to 3300000
[   83.839952] rockchip-iodomain fdc20000.syscon:io-domains: Setting to 3300000 done
[   83.855358] mmc_host mmc1: Bus speed (slot 0) = 375000Hz (slot req 400000Hz, actual 375000HZ div = 0)
[   84.153827] rockchip-iodomain fdc20000.syscon:io-domains: Setting to 3300000
[   84.154524] rockchip-iodomain fdc20000.syscon:io-domains: Setting to 3300000 done
[   84.156149] rockchip-iodomain fdc20000.syscon:io-domains: Setting to 1800000
[   84.156838] rockchip-iodomain fdc20000.syscon:io-domains: Setting to 1800000 done
[   84.183932] mmc_host mmc1: Bus speed (slot 0) = 150000000Hz (slot req 150000000Hz, actual 150000000HZ div = 0)
[   84.202888] dwmmc_rockchip fe2b0000.mmc: Successfully tuned phase to 257
[   84.203574] mmc1: new ultra high speed SDR104 SDXC card at address aaaa
[   84.205537] mmcblk1: mmc1:aaaa SD64G 59.5 GiB
[   84.211434]  mmcblk1: p1

sd-uhs-ddr50 should also work based on my testing.

Regards,
Jonas

> +	vmmc-supply = <&vcc3v3_sys>;
> +	vqmmc-supply = <&vccio_sd>;
> +	status = "okay";
> +};
> +

[snip]

Re: [PATCH v2 0/2] arm64: dts: rockchip: Add Radxa ROCK 3C

[Rob Herring]

On Sun, 28 Apr 2024 20:36:16 +0800, Chukun Pan wrote:
> Changes in v2:
>   Collected Acked-by.
>   Drop cd-gpios for sdhci.
>   Add mmc-hs200-1_8v to eMMC.
>   Correct the spi max frequency.
>   Update model name and compatible.
>   Update regulator according to the schematic.
> 
> Chukun Pan (2):
>   dt-bindings: arm: rockchip: add Radxa ROCK 3C
>   arm64: dts: rockchip: Add Radxa ROCK 3C
> 
>  .../devicetree/bindings/arm/rockchip.yaml     |   5 +
>  arch/arm64/boot/dts/rockchip/Makefile         |   1 +
>  .../boot/dts/rockchip/rk3566-rock-3c.dts      | 750 ++++++++++++++++++
>  3 files changed, 756 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-rock-3c.dts
> 
> --
> 2.25.1
> 
> 
> 


My bot found new DTB warnings on the .dts files added or changed in this
series.

Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings
are fixed by another series. Ultimately, it is up to the platform
maintainer whether these warnings are acceptable or not. No need to reply
unless the platform maintainer has comments.

If you already ran DT checks and didn't see these error(s), then
make sure dt-schema is up to date:

  pip3 install dtschema --upgrade


New warnings running 'make CHECK_DTBS=y rockchip/rk3566-rock-3c.dtb' for 20240428123618.72170-1-amadeus@jmu.edu.cn:

arch/arm64/boot/dts/rockchip/rk3566-rock-3c.dtb: pmic@20: '#sound-dai-cells', 'assigned-clock-parents', 'assigned-clocks', 'clock-names', 'clocks', 'codec' do not match any of the regexes: 'pinctrl-[0-9]+'
	from schema $id: http://devicetree.org/schemas/mfd/rockchip,rk809.yaml#

Re: [PATCH v2 0/2] arm64: dts: rockchip: Add Radxa ROCK 3C

[Heiko Stuebner]

On Sun, 28 Apr 2024 20:36:16 +0800, Chukun Pan wrote:
> Changes in v2:
>   Collected Acked-by.
>   Drop cd-gpios for sdhci.
>   Add mmc-hs200-1_8v to eMMC.
>   Correct the spi max frequency.
>   Update model name and compatible.
>   Update regulator according to the schematic.
> 
> [...]

Applied, thanks!

[1/2] dt-bindings: arm: rockchip: add Radxa ROCK 3C
      commit: c0c153e341d2a82241bf0a0b78117ceeb29be3eb
[2/2] arm64: dts: rockchip: Add Radxa ROCK 3C
      commit: ee219017ddb50be14c60d3cbe3e51ac0b2008d40

Best regards,
-- 
Heiko Stuebner <heiko@sntech.de>

Re: [PATCH v2 0/2] arm64: dts: rockchip: Add Radxa ROCK 3C

[Heiko Stübner]

Am Freitag, 3. Mai 2024, 13:38:19 CEST schrieb Heiko Stuebner:
> On Sun, 28 Apr 2024 20:36:16 +0800, Chukun Pan wrote:
> > Changes in v2:
> >   Collected Acked-by.
> >   Drop cd-gpios for sdhci.
> >   Add mmc-hs200-1_8v to eMMC.
> >   Correct the spi max frequency.
> >   Update model name and compatible.
> >   Update regulator according to the schematic.
> > 
> > [...]
> 
> Applied, thanks!
> 
> [1/2] dt-bindings: arm: rockchip: add Radxa ROCK 3C
>       commit: c0c153e341d2a82241bf0a0b78117ceeb29be3eb
> [2/2] arm64: dts: rockchip: Add Radxa ROCK 3C
>       commit: ee219017ddb50be14c60d3cbe3e51ac0b2008d40

Forgot to add, I've dropped the rk809-sound node, as well as the sound-related
properties from the rk809 pmic that got flagged by the binding check
and which I could reproduce here too.

So please submit these as follow up patches, once the necessary changes
to the pmic to allow its codec use are merged.


Thanks
Heiko