* [PATCH v3 1/4] dt-bindings: media: Describe Qualcomm SM8650 CAMSS IP
2025-10-17 3:11 [PATCH v3 0/4] media: qcom: camss: Add Qualcomm SM8650 CAMSS support Vladimir Zapolskiy
@ 2025-10-17 3:11 ` Vladimir Zapolskiy
2025-10-22 6:46 ` Krzysztof Kozlowski
2025-10-23 15:08 ` Bryan O'Donoghue
2025-10-17 3:11 ` [PATCH v3 2/4] media: qcom: camss: Add Qualcomm SM8650 CAMSS support Vladimir Zapolskiy
` (3 subsequent siblings)
4 siblings, 2 replies; 11+ messages in thread
From: Vladimir Zapolskiy @ 2025-10-17 3:11 UTC (permalink / raw)
To: Bryan O'Donoghue, Robert Foss, Todor Tomov,
Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Bjorn Andersson, Konrad Dybcio
Cc: Neil Armstrong, linux-arm-msm, linux-media, devicetree
Add device tree bindings for Qualcomm SM8650 camera subsystem.
Qualcomm SM8650 CAMSS IP contains the next subdevices:
* 6 x CSIPHY,
* 3 x CSID, 2 x CSID Lite,
* 3 x IFE, 2 x IFE Lite.
Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
---
.../bindings/media/qcom,sm8650-camss.yaml | 375 ++++++++++++++++++
1 file changed, 375 insertions(+)
create mode 100644 Documentation/devicetree/bindings/media/qcom,sm8650-camss.yaml
diff --git a/Documentation/devicetree/bindings/media/qcom,sm8650-camss.yaml b/Documentation/devicetree/bindings/media/qcom,sm8650-camss.yaml
new file mode 100644
index 000000000000..9c8de722601e
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/qcom,sm8650-camss.yaml
@@ -0,0 +1,375 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/qcom,sm8650-camss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SM8650 Camera Subsystem (CAMSS)
+
+maintainers:
+ - Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
+
+description:
+ The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms.
+
+properties:
+ compatible:
+ const: qcom,sm8650-camss
+
+ reg:
+ maxItems: 17
+
+ reg-names:
+ items:
+ - const: csid_wrapper
+ - const: csid0
+ - const: csid1
+ - const: csid2
+ - const: csid_lite0
+ - const: csid_lite1
+ - const: csiphy0
+ - const: csiphy1
+ - const: csiphy2
+ - const: csiphy3
+ - const: csiphy4
+ - const: csiphy5
+ - const: vfe0
+ - const: vfe1
+ - const: vfe2
+ - const: vfe_lite0
+ - const: vfe_lite1
+
+ clocks:
+ maxItems: 33
+
+ clock-names:
+ items:
+ - const: camnoc_axi
+ - const: cpas_ahb
+ - const: cpas_fast_ahb
+ - const: cpas_vfe0
+ - const: cpas_vfe1
+ - const: cpas_vfe2
+ - const: cpas_vfe_lite
+ - const: csid
+ - const: csiphy0
+ - const: csiphy0_timer
+ - const: csiphy1
+ - const: csiphy1_timer
+ - const: csiphy2
+ - const: csiphy2_timer
+ - const: csiphy3
+ - const: csiphy3_timer
+ - const: csiphy4
+ - const: csiphy4_timer
+ - const: csiphy5
+ - const: csiphy5_timer
+ - const: csiphy_rx
+ - const: gcc_axi_hf
+ - const: qdss_debug_xo
+ - const: vfe0
+ - const: vfe0_fast_ahb
+ - const: vfe1
+ - const: vfe1_fast_ahb
+ - const: vfe2
+ - const: vfe2_fast_ahb
+ - const: vfe_lite
+ - const: vfe_lite_ahb
+ - const: vfe_lite_cphy_rx
+ - const: vfe_lite_csid
+
+ interrupts:
+ maxItems: 16
+
+ interrupt-names:
+ items:
+ - const: csid0
+ - const: csid1
+ - const: csid2
+ - const: csid_lite0
+ - const: csid_lite1
+ - const: csiphy0
+ - const: csiphy1
+ - const: csiphy2
+ - const: csiphy3
+ - const: csiphy4
+ - const: csiphy5
+ - const: vfe0
+ - const: vfe1
+ - const: vfe2
+ - const: vfe_lite0
+ - const: vfe_lite1
+
+ interconnects:
+ maxItems: 2
+
+ interconnect-names:
+ items:
+ - const: ahb
+ - const: hf_mnoc
+
+ iommus:
+ maxItems: 3
+
+ power-domains:
+ items:
+ - description: IFE0 GDSC - Image Front End, Global Distributed Switch Controller.
+ - description: IFE1 GDSC - Image Front End, Global Distributed Switch Controller.
+ - description: IFE2 GDSC - Image Front End, Global Distributed Switch Controller.
+ - description: Titan GDSC - Titan ISP Block, Global Distributed Switch Controller.
+
+ power-domain-names:
+ items:
+ - const: ife0
+ - const: ife1
+ - const: ife2
+ - const: top
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+
+ description:
+ CSI input ports.
+
+ patternProperties:
+ "^port@[0-5]$":
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+
+ description:
+ Input port for receiving CSI data from a CSIPHY.
+
+ properties:
+ endpoint:
+ $ref: video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ data-lanes:
+ minItems: 1
+ maxItems: 4
+
+ bus-type:
+ enum:
+ - 1 # MEDIA_BUS_TYPE_CSI2_CPHY
+ - 4 # MEDIA_BUS_TYPE_CSI2_DPHY
+
+ required:
+ - data-lanes
+
+ vdd-csiphy01-0p9-supply:
+ description:
+ Phandle to a 0.9V regulator supply to CSIPHY0 and CSIPHY1 IP blocks.
+
+ vdd-csiphy01-1p2-supply:
+ description:
+ Phandle to a 1.2V regulator supply to CSIPHY0 and CSIPHY1 IP blocks.
+
+ vdd-csiphy24-0p9-supply:
+ description:
+ Phandle to a 0.9V regulator supply to CSIPHY2 and CSIPHY4 IP blocks.
+
+ vdd-csiphy24-1p2-supply:
+ description:
+ Phandle to a 1.2V regulator supply to CSIPHY2 and CSIPHY4 IP blocks.
+
+ vdd-csiphy35-0p9-supply:
+ description:
+ Phandle to a 0.9V regulator supply to CSIPHY3 and CSIPHY5 IP blocks.
+
+ vdd-csiphy35-1p2-supply:
+ description:
+ Phandle to a 1.2V regulator supply to CSIPHY3 and CSIPHY5 IP blocks.
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - clocks
+ - clock-names
+ - interconnects
+ - interconnect-names
+ - interrupts
+ - interrupt-names
+ - iommus
+ - power-domains
+ - power-domain-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,sm8650-camcc.h>
+ #include <dt-bindings/clock/qcom,sm8650-gcc.h>
+ #include <dt-bindings/interconnect/qcom,sm8650-rpmh.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ isp@acb6000 {
+ compatible = "qcom,sm8650-camss";
+ reg = <0 0x0acb6000 0 0x1000>,
+ <0 0x0acb8000 0 0x1000>,
+ <0 0x0acba000 0 0x1000>,
+ <0 0x0acbc000 0 0x1000>,
+ <0 0x0accb000 0 0x1000>,
+ <0 0x0acd0000 0 0x1000>,
+ <0 0x0ace4000 0 0x2000>,
+ <0 0x0ace6000 0 0x2000>,
+ <0 0x0ace8000 0 0x2000>,
+ <0 0x0acea000 0 0x2000>,
+ <0 0x0acec000 0 0x2000>,
+ <0 0x0acee000 0 0x2000>,
+ <0 0x0ac62000 0 0xf000>,
+ <0 0x0ac71000 0 0xf000>,
+ <0 0x0ac80000 0 0xf000>,
+ <0 0x0accc000 0 0x2000>,
+ <0 0x0acd1000 0 0x2000>;
+ reg-names = "csid_wrapper",
+ "csid0",
+ "csid1",
+ "csid2",
+ "csid_lite0",
+ "csid_lite1",
+ "csiphy0",
+ "csiphy1",
+ "csiphy2",
+ "csiphy3",
+ "csiphy4",
+ "csiphy5",
+ "vfe0",
+ "vfe1",
+ "vfe2",
+ "vfe_lite0",
+ "vfe_lite1";
+ clocks = <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>,
+ <&camcc CAM_CC_CPAS_AHB_CLK>,
+ <&camcc CAM_CC_CPAS_FAST_AHB_CLK>,
+ <&camcc CAM_CC_CPAS_IFE_0_CLK>,
+ <&camcc CAM_CC_CPAS_IFE_1_CLK>,
+ <&camcc CAM_CC_CPAS_IFE_2_CLK>,
+ <&camcc CAM_CC_CPAS_IFE_LITE_CLK>,
+ <&camcc CAM_CC_CSID_CLK>,
+ <&camcc CAM_CC_CSIPHY0_CLK>,
+ <&camcc CAM_CC_CSI0PHYTIMER_CLK>,
+ <&camcc CAM_CC_CSI1PHYTIMER_CLK>,
+ <&camcc CAM_CC_CSIPHY1_CLK>,
+ <&camcc CAM_CC_CSI2PHYTIMER_CLK>,
+ <&camcc CAM_CC_CSIPHY2_CLK>,
+ <&camcc CAM_CC_CSI3PHYTIMER_CLK>,
+ <&camcc CAM_CC_CSIPHY3_CLK>,
+ <&camcc CAM_CC_CSI4PHYTIMER_CLK>,
+ <&camcc CAM_CC_CSIPHY4_CLK>,
+ <&camcc CAM_CC_CSI5PHYTIMER_CLK>,
+ <&camcc CAM_CC_CSIPHY5_CLK>,
+ <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>,
+ <&gcc GCC_CAMERA_HF_AXI_CLK>,
+ <&camcc CAM_CC_QDSS_DEBUG_XO_CLK>,
+ <&camcc CAM_CC_IFE_0_CLK>,
+ <&camcc CAM_CC_IFE_0_FAST_AHB_CLK>,
+ <&camcc CAM_CC_IFE_1_CLK>,
+ <&camcc CAM_CC_IFE_1_FAST_AHB_CLK>,
+ <&camcc CAM_CC_IFE_2_CLK>,
+ <&camcc CAM_CC_IFE_2_FAST_AHB_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CLK>,
+ <&camcc CAM_CC_IFE_LITE_AHB_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CSID_CLK>;
+ clock-names = "camnoc_axi",
+ "cpas_ahb",
+ "cpas_fast_ahb",
+ "cpas_vfe0",
+ "cpas_vfe1",
+ "cpas_vfe2",
+ "cpas_vfe_lite",
+ "csid",
+ "csiphy0",
+ "csiphy0_timer",
+ "csiphy1",
+ "csiphy1_timer",
+ "csiphy2",
+ "csiphy2_timer",
+ "csiphy3",
+ "csiphy3_timer",
+ "csiphy4",
+ "csiphy4_timer",
+ "csiphy5",
+ "csiphy5_timer",
+ "csiphy_rx",
+ "gcc_axi_hf",
+ "qdss_debug_xo",
+ "vfe0",
+ "vfe0_fast_ahb",
+ "vfe1",
+ "vfe1_fast_ahb",
+ "vfe2",
+ "vfe2_fast_ahb",
+ "vfe_lite",
+ "vfe_lite_ahb",
+ "vfe_lite_cphy_rx",
+ "vfe_lite_csid";
+ interrupts = <GIC_SPI 601 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 603 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 431 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 605 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 376 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 602 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 604 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 688 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 606 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 377 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "csid0",
+ "csid1",
+ "csid2",
+ "csid_lite0",
+ "csid_lite1",
+ "csiphy0",
+ "csiphy1",
+ "csiphy2",
+ "csiphy3",
+ "csiphy4",
+ "csiphy5",
+ "vfe0",
+ "vfe1",
+ "vfe2",
+ "vfe_lite0",
+ "vfe_lite1";
+ interconnects = <&gem_noc MASTER_APPSS_PROC 0
+ &config_noc SLAVE_CAMERA_CFG 0>,
+ <&mmss_noc MASTER_CAMNOC_HF 0
+ &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "ahb", "hf_mnoc";
+ iommus = <&apps_smmu 0x800 0x20>,
+ <&apps_smmu 0x18a0 0x40>,
+ <&apps_smmu 0x1860 0x00>;
+ power-domains = <&camcc CAM_CC_IFE_0_GDSC>,
+ <&camcc CAM_CC_IFE_1_GDSC>,
+ <&camcc CAM_CC_IFE_2_GDSC>,
+ <&camcc CAM_CC_TITAN_TOP_GDSC>;
+ power-domain-names = "ife0", "ife1", "ife2", "top";
+ vdd-csiphy01-0p9-supply = <&vreg_0p9>;
+ vdd-csiphy01-1p2-supply = <&vreg_1p2>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ reg = <1>;
+
+ csiphy1_ep: endpoint {
+ data-lanes = <0 1>;
+ remote-endpoint = <&camera_sensor>;
+ };
+ };
+ };
+ };
+ };
--
2.49.0
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [PATCH v3 1/4] dt-bindings: media: Describe Qualcomm SM8650 CAMSS IP
2025-10-17 3:11 ` [PATCH v3 1/4] dt-bindings: media: Describe Qualcomm SM8650 CAMSS IP Vladimir Zapolskiy
@ 2025-10-22 6:46 ` Krzysztof Kozlowski
2025-10-23 15:08 ` Bryan O'Donoghue
1 sibling, 0 replies; 11+ messages in thread
From: Krzysztof Kozlowski @ 2025-10-22 6:46 UTC (permalink / raw)
To: Vladimir Zapolskiy
Cc: Bryan O'Donoghue, Robert Foss, Todor Tomov,
Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Bjorn Andersson, Konrad Dybcio, Neil Armstrong,
linux-arm-msm, linux-media, devicetree
On Fri, Oct 17, 2025 at 06:11:28AM +0300, Vladimir Zapolskiy wrote:
> Add device tree bindings for Qualcomm SM8650 camera subsystem.
>
> Qualcomm SM8650 CAMSS IP contains the next subdevices:
> * 6 x CSIPHY,
> * 3 x CSID, 2 x CSID Lite,
> * 3 x IFE, 2 x IFE Lite.
>
> Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
> ---
> .../bindings/media/qcom,sm8650-camss.yaml | 375 ++++++++++++++++++
> 1 file changed, 375 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/media/qcom,sm8650-camss.yaml
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v3 1/4] dt-bindings: media: Describe Qualcomm SM8650 CAMSS IP
2025-10-17 3:11 ` [PATCH v3 1/4] dt-bindings: media: Describe Qualcomm SM8650 CAMSS IP Vladimir Zapolskiy
2025-10-22 6:46 ` Krzysztof Kozlowski
@ 2025-10-23 15:08 ` Bryan O'Donoghue
1 sibling, 0 replies; 11+ messages in thread
From: Bryan O'Donoghue @ 2025-10-23 15:08 UTC (permalink / raw)
To: Vladimir Zapolskiy, Robert Foss, Todor Tomov,
Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Bjorn Andersson, Konrad Dybcio
Cc: Neil Armstrong, linux-arm-msm, linux-media, devicetree
On 17/10/2025 04:11, Vladimir Zapolskiy wrote:
> Add device tree bindings for Qualcomm SM8650 camera subsystem.
>
> Qualcomm SM8650 CAMSS IP contains the next subdevices:
> * 6 x CSIPHY,
> * 3 x CSID, 2 x CSID Lite,
> * 3 x IFE, 2 x IFE Lite.
>
> Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
> ---
> .../bindings/media/qcom,sm8650-camss.yaml | 375 ++++++++++++++++++
> 1 file changed, 375 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/media/qcom,sm8650-camss.yaml
>
> diff --git a/Documentation/devicetree/bindings/media/qcom,sm8650-camss.yaml b/Documentation/devicetree/bindings/media/qcom,sm8650-camss.yaml
> new file mode 100644
> index 000000000000..9c8de722601e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/media/qcom,sm8650-camss.yaml
> @@ -0,0 +1,375 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/media/qcom,sm8650-camss.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm SM8650 Camera Subsystem (CAMSS)
> +
> +maintainers:
> + - Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
> +
> +description:
> + The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms.
> +
> +properties:
> + compatible:
> + const: qcom,sm8650-camss
> +
> + reg:
> + maxItems: 17
> +
> + reg-names:
> + items:
> + - const: csid_wrapper
> + - const: csid0
> + - const: csid1
> + - const: csid2
> + - const: csid_lite0
> + - const: csid_lite1
> + - const: csiphy0
> + - const: csiphy1
> + - const: csiphy2
> + - const: csiphy3
> + - const: csiphy4
> + - const: csiphy5
> + - const: vfe0
> + - const: vfe1
> + - const: vfe2
> + - const: vfe_lite0
> + - const: vfe_lite1
> +
> + clocks:
> + maxItems: 33
> +
> + clock-names:
> + items:
> + - const: camnoc_axi
> + - const: cpas_ahb
> + - const: cpas_fast_ahb
> + - const: cpas_vfe0
> + - const: cpas_vfe1
> + - const: cpas_vfe2
> + - const: cpas_vfe_lite
> + - const: csid
> + - const: csiphy0
> + - const: csiphy0_timer
> + - const: csiphy1
> + - const: csiphy1_timer
> + - const: csiphy2
> + - const: csiphy2_timer
> + - const: csiphy3
> + - const: csiphy3_timer
> + - const: csiphy4
> + - const: csiphy4_timer
> + - const: csiphy5
> + - const: csiphy5_timer
> + - const: csiphy_rx
> + - const: gcc_axi_hf
> + - const: qdss_debug_xo
> + - const: vfe0
> + - const: vfe0_fast_ahb
> + - const: vfe1
> + - const: vfe1_fast_ahb
> + - const: vfe2
> + - const: vfe2_fast_ahb
> + - const: vfe_lite
> + - const: vfe_lite_ahb
> + - const: vfe_lite_cphy_rx
> + - const: vfe_lite_csid
> +
> + interrupts:
> + maxItems: 16
> +
> + interrupt-names:
> + items:
> + - const: csid0
> + - const: csid1
> + - const: csid2
> + - const: csid_lite0
> + - const: csid_lite1
> + - const: csiphy0
> + - const: csiphy1
> + - const: csiphy2
> + - const: csiphy3
> + - const: csiphy4
> + - const: csiphy5
> + - const: vfe0
> + - const: vfe1
> + - const: vfe2
> + - const: vfe_lite0
> + - const: vfe_lite1
> +
> + interconnects:
> + maxItems: 2
> +
> + interconnect-names:
> + items:
> + - const: ahb
> + - const: hf_mnoc
> +
> + iommus:
> + maxItems: 3
> +
> + power-domains:
> + items:
> + - description: IFE0 GDSC - Image Front End, Global Distributed Switch Controller.
> + - description: IFE1 GDSC - Image Front End, Global Distributed Switch Controller.
> + - description: IFE2 GDSC - Image Front End, Global Distributed Switch Controller.
> + - description: Titan GDSC - Titan ISP Block, Global Distributed Switch Controller.
> +
> + power-domain-names:
> + items:
> + - const: ife0
> + - const: ife1
> + - const: ife2
> + - const: top
> +
> + ports:
> + $ref: /schemas/graph.yaml#/properties/ports
> +
> + description:
> + CSI input ports.
> +
> + patternProperties:
> + "^port@[0-5]$":
> + $ref: /schemas/graph.yaml#/$defs/port-base
> + unevaluatedProperties: false
> +
> + description:
> + Input port for receiving CSI data from a CSIPHY.
> +
> + properties:
> + endpoint:
> + $ref: video-interfaces.yaml#
> + unevaluatedProperties: false
> +
> + properties:
> + data-lanes:
> + minItems: 1
> + maxItems: 4
> +
> + bus-type:
> + enum:
> + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY
> + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY
> +
> + required:
> + - data-lanes
> +
> + vdd-csiphy01-0p9-supply:
> + description:
> + Phandle to a 0.9V regulator supply to CSIPHY0 and CSIPHY1 IP blocks.
> +
> + vdd-csiphy01-1p2-supply:
> + description:
> + Phandle to a 1.2V regulator supply to CSIPHY0 and CSIPHY1 IP blocks.
> +
> + vdd-csiphy24-0p9-supply:
> + description:
> + Phandle to a 0.9V regulator supply to CSIPHY2 and CSIPHY4 IP blocks.
> +
> + vdd-csiphy24-1p2-supply:
> + description:
> + Phandle to a 1.2V regulator supply to CSIPHY2 and CSIPHY4 IP blocks.
> +
> + vdd-csiphy35-0p9-supply:
> + description:
> + Phandle to a 0.9V regulator supply to CSIPHY3 and CSIPHY5 IP blocks.
> +
> + vdd-csiphy35-1p2-supply:
> + description:
> + Phandle to a 1.2V regulator supply to CSIPHY3 and CSIPHY5 IP blocks.
> +
> +required:
> + - compatible
> + - reg
> + - reg-names
> + - clocks
> + - clock-names
> + - interconnects
> + - interconnect-names
> + - interrupts
> + - interrupt-names
> + - iommus
> + - power-domains
> + - power-domain-names
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/qcom,sm8650-camcc.h>
> + #include <dt-bindings/clock/qcom,sm8650-gcc.h>
> + #include <dt-bindings/interconnect/qcom,sm8650-rpmh.h>
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + isp@acb6000 {
> + compatible = "qcom,sm8650-camss";
> + reg = <0 0x0acb6000 0 0x1000>,
> + <0 0x0acb8000 0 0x1000>,
> + <0 0x0acba000 0 0x1000>,
> + <0 0x0acbc000 0 0x1000>,
> + <0 0x0accb000 0 0x1000>,
> + <0 0x0acd0000 0 0x1000>,
> + <0 0x0ace4000 0 0x2000>,
> + <0 0x0ace6000 0 0x2000>,
> + <0 0x0ace8000 0 0x2000>,
> + <0 0x0acea000 0 0x2000>,
> + <0 0x0acec000 0 0x2000>,
> + <0 0x0acee000 0 0x2000>,
> + <0 0x0ac62000 0 0xf000>,
> + <0 0x0ac71000 0 0xf000>,
> + <0 0x0ac80000 0 0xf000>,
> + <0 0x0accc000 0 0x2000>,
> + <0 0x0acd1000 0 0x2000>;
> + reg-names = "csid_wrapper",
> + "csid0",
> + "csid1",
> + "csid2",
> + "csid_lite0",
> + "csid_lite1",
> + "csiphy0",
> + "csiphy1",
> + "csiphy2",
> + "csiphy3",
> + "csiphy4",
> + "csiphy5",
> + "vfe0",
> + "vfe1",
> + "vfe2",
> + "vfe_lite0",
> + "vfe_lite1";
> + clocks = <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>,
> + <&camcc CAM_CC_CPAS_AHB_CLK>,
> + <&camcc CAM_CC_CPAS_FAST_AHB_CLK>,
> + <&camcc CAM_CC_CPAS_IFE_0_CLK>,
> + <&camcc CAM_CC_CPAS_IFE_1_CLK>,
> + <&camcc CAM_CC_CPAS_IFE_2_CLK>,
> + <&camcc CAM_CC_CPAS_IFE_LITE_CLK>,
> + <&camcc CAM_CC_CSID_CLK>,
> + <&camcc CAM_CC_CSIPHY0_CLK>,
> + <&camcc CAM_CC_CSI0PHYTIMER_CLK>,
> + <&camcc CAM_CC_CSI1PHYTIMER_CLK>,
> + <&camcc CAM_CC_CSIPHY1_CLK>,
> + <&camcc CAM_CC_CSI2PHYTIMER_CLK>,
> + <&camcc CAM_CC_CSIPHY2_CLK>,
> + <&camcc CAM_CC_CSI3PHYTIMER_CLK>,
> + <&camcc CAM_CC_CSIPHY3_CLK>,
> + <&camcc CAM_CC_CSI4PHYTIMER_CLK>,
> + <&camcc CAM_CC_CSIPHY4_CLK>,
> + <&camcc CAM_CC_CSI5PHYTIMER_CLK>,
> + <&camcc CAM_CC_CSIPHY5_CLK>,
> + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>,
> + <&gcc GCC_CAMERA_HF_AXI_CLK>,
> + <&camcc CAM_CC_QDSS_DEBUG_XO_CLK>,
> + <&camcc CAM_CC_IFE_0_CLK>,
> + <&camcc CAM_CC_IFE_0_FAST_AHB_CLK>,
> + <&camcc CAM_CC_IFE_1_CLK>,
> + <&camcc CAM_CC_IFE_1_FAST_AHB_CLK>,
> + <&camcc CAM_CC_IFE_2_CLK>,
> + <&camcc CAM_CC_IFE_2_FAST_AHB_CLK>,
> + <&camcc CAM_CC_IFE_LITE_CLK>,
> + <&camcc CAM_CC_IFE_LITE_AHB_CLK>,
> + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
> + <&camcc CAM_CC_IFE_LITE_CSID_CLK>;
> + clock-names = "camnoc_axi",
> + "cpas_ahb",
> + "cpas_fast_ahb",
> + "cpas_vfe0",
> + "cpas_vfe1",
> + "cpas_vfe2",
> + "cpas_vfe_lite",
> + "csid",
> + "csiphy0",
> + "csiphy0_timer",
> + "csiphy1",
> + "csiphy1_timer",
> + "csiphy2",
> + "csiphy2_timer",
> + "csiphy3",
> + "csiphy3_timer",
> + "csiphy4",
> + "csiphy4_timer",
> + "csiphy5",
> + "csiphy5_timer",
> + "csiphy_rx",
> + "gcc_axi_hf",
> + "qdss_debug_xo",
> + "vfe0",
> + "vfe0_fast_ahb",
> + "vfe1",
> + "vfe1_fast_ahb",
> + "vfe2",
> + "vfe2_fast_ahb",
> + "vfe_lite",
> + "vfe_lite_ahb",
> + "vfe_lite_cphy_rx",
> + "vfe_lite_csid";
> + interrupts = <GIC_SPI 601 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 603 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 431 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 605 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 376 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 602 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 604 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 688 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 606 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 377 IRQ_TYPE_EDGE_RISING>;
> + interrupt-names = "csid0",
> + "csid1",
> + "csid2",
> + "csid_lite0",
> + "csid_lite1",
> + "csiphy0",
> + "csiphy1",
> + "csiphy2",
> + "csiphy3",
> + "csiphy4",
> + "csiphy5",
> + "vfe0",
> + "vfe1",
> + "vfe2",
> + "vfe_lite0",
> + "vfe_lite1";
> + interconnects = <&gem_noc MASTER_APPSS_PROC 0
> + &config_noc SLAVE_CAMERA_CFG 0>,
> + <&mmss_noc MASTER_CAMNOC_HF 0
> + &mc_virt SLAVE_EBI1 0>;
> + interconnect-names = "ahb", "hf_mnoc";
> + iommus = <&apps_smmu 0x800 0x20>,
> + <&apps_smmu 0x18a0 0x40>,
> + <&apps_smmu 0x1860 0x00>;
> + power-domains = <&camcc CAM_CC_IFE_0_GDSC>,
> + <&camcc CAM_CC_IFE_1_GDSC>,
> + <&camcc CAM_CC_IFE_2_GDSC>,
> + <&camcc CAM_CC_TITAN_TOP_GDSC>;
> + power-domain-names = "ife0", "ife1", "ife2", "top";
> + vdd-csiphy01-0p9-supply = <&vreg_0p9>;
> + vdd-csiphy01-1p2-supply = <&vreg_1p2>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@1 {
> + reg = <1>;
> +
> + csiphy1_ep: endpoint {
> + data-lanes = <0 1>;
> + remote-endpoint = <&camera_sensor>;
> + };
> + };
> + };
> + };
> + };
> --
> 2.49.0
>
I don't think the squashing down of \n is necesary.
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v3 2/4] media: qcom: camss: Add Qualcomm SM8650 CAMSS support
2025-10-17 3:11 [PATCH v3 0/4] media: qcom: camss: Add Qualcomm SM8650 CAMSS support Vladimir Zapolskiy
2025-10-17 3:11 ` [PATCH v3 1/4] dt-bindings: media: Describe Qualcomm SM8650 CAMSS IP Vladimir Zapolskiy
@ 2025-10-17 3:11 ` Vladimir Zapolskiy
2025-10-23 15:10 ` Bryan O'Donoghue
2025-10-17 3:11 ` [PATCH v3 3/4] media: qcom: camss: Add CSIPHY 2.2.0 lane configuration for SM8650 Vladimir Zapolskiy
` (2 subsequent siblings)
4 siblings, 1 reply; 11+ messages in thread
From: Vladimir Zapolskiy @ 2025-10-17 3:11 UTC (permalink / raw)
To: Bryan O'Donoghue, Robert Foss, Todor Tomov,
Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Bjorn Andersson, Konrad Dybcio
Cc: Neil Armstrong, linux-arm-msm, linux-media, devicetree
Add the basic support of CAMSS IP on Qualcomm SM8650 SoC powered boards.
SM8650 CAMSS provides:
- 6 x CSIPHY,
- 3 x CSID, 2 x CSID Lite,
- 3 x VFE, 2 x VFE Lite.
Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
---
drivers/media/platform/qcom/camss/camss-vfe.c | 2 +
drivers/media/platform/qcom/camss/camss.c | 326 ++++++++++++++++++
drivers/media/platform/qcom/camss/camss.h | 1 +
3 files changed, 329 insertions(+)
diff --git a/drivers/media/platform/qcom/camss/camss-vfe.c b/drivers/media/platform/qcom/camss/camss-vfe.c
index dff8d0a1e8c2..f76bcf69159a 100644
--- a/drivers/media/platform/qcom/camss/camss-vfe.c
+++ b/drivers/media/platform/qcom/camss/camss-vfe.c
@@ -348,6 +348,7 @@ static u32 vfe_src_pad_code(struct vfe_line *line, u32 sink_code,
case CAMSS_8300:
case CAMSS_845:
case CAMSS_8550:
+ case CAMSS_8650:
case CAMSS_8775P:
case CAMSS_X1E80100:
switch (sink_code) {
@@ -1995,6 +1996,7 @@ static int vfe_bpl_align(struct vfe_device *vfe)
case CAMSS_8300:
case CAMSS_845:
case CAMSS_8550:
+ case CAMSS_8650:
case CAMSS_8775P:
case CAMSS_X1E80100:
ret = 16;
diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c
index 2fbcd0e343aa..06a184fb9ae3 100644
--- a/drivers/media/platform/qcom/camss/camss.c
+++ b/drivers/media/platform/qcom/camss/camss.c
@@ -2617,6 +2617,317 @@ static const struct resources_icc icc_res_sm8550[] = {
},
};
+static const struct camss_subdev_resources csiphy_res_sm8650[] = {
+ /* CSIPHY0 */
+ {
+ .regulators = { "vdd-csiphy01-0p9", "vdd-csiphy01-1p2", },
+ .clock = { "csiphy0", "csiphy0_timer" },
+ .clock_rate = { { 400000000 },
+ { 400000000 } },
+ .reg = { "csiphy0" },
+ .interrupt = { "csiphy0" },
+ .csiphy = {
+ .id = 0,
+ .hw_ops = &csiphy_ops_3ph_1_0,
+ .formats = &csiphy_formats_sdm845,
+ },
+ },
+ /* CSIPHY1 */
+ {
+ .regulators = { "vdd-csiphy01-0p9", "vdd-csiphy01-1p2", },
+ .clock = { "csiphy1", "csiphy1_timer" },
+ .clock_rate = { { 400000000 },
+ { 400000000 } },
+ .reg = { "csiphy1" },
+ .interrupt = { "csiphy1" },
+ .csiphy = {
+ .id = 1,
+ .hw_ops = &csiphy_ops_3ph_1_0,
+ .formats = &csiphy_formats_sdm845,
+ },
+ },
+ /* CSIPHY2 */
+ {
+ .regulators = { "vdd-csiphy24-0p9", "vdd-csiphy24-1p2", },
+ .clock = { "csiphy2", "csiphy2_timer" },
+ .clock_rate = { { 400000000 },
+ { 400000000 } },
+ .reg = { "csiphy2" },
+ .interrupt = { "csiphy2" },
+ .csiphy = {
+ .id = 2,
+ .hw_ops = &csiphy_ops_3ph_1_0,
+ .formats = &csiphy_formats_sdm845,
+ },
+ },
+ /* CSIPHY3 */
+ {
+ .regulators = { "vdd-csiphy35-0p9", "vdd-csiphy35-1p2", },
+ .clock = { "csiphy3", "csiphy3_timer" },
+ .clock_rate = { { 400000000 },
+ { 400000000 } },
+ .reg = { "csiphy3" },
+ .interrupt = { "csiphy3" },
+ .csiphy = {
+ .id = 3,
+ .hw_ops = &csiphy_ops_3ph_1_0,
+ .formats = &csiphy_formats_sdm845,
+ },
+ },
+ /* CSIPHY4 */
+ {
+ .regulators = { "vdd-csiphy24-0p9", "vdd-csiphy24-1p2", },
+ .clock = { "csiphy4", "csiphy4_timer" },
+ .clock_rate = { { 400000000 },
+ { 400000000 } },
+ .reg = { "csiphy4" },
+ .interrupt = { "csiphy4" },
+ .csiphy = {
+ .id = 4,
+ .hw_ops = &csiphy_ops_3ph_1_0,
+ .formats = &csiphy_formats_sdm845,
+ },
+ },
+ /* CSIPHY5 */
+ {
+ .regulators = { "vdd-csiphy35-0p9", "vdd-csiphy35-1p2", },
+ .clock = { "csiphy5", "csiphy5_timer" },
+ .clock_rate = { { 400000000 },
+ { 400000000 } },
+ .reg = { "csiphy5" },
+ .interrupt = { "csiphy5" },
+ .csiphy = {
+ .id = 5,
+ .hw_ops = &csiphy_ops_3ph_1_0,
+ .formats = &csiphy_formats_sdm845,
+ },
+ },
+};
+
+static const struct camss_subdev_resources csid_res_sm8650[] = {
+ /* CSID0 */
+ {
+ .regulators = { },
+ .clock = { "csid", "csiphy_rx" },
+ .clock_rate = { { 400000000 },
+ { 400000000, 480000000 } },
+ .reg = { "csid0" },
+ .interrupt = { "csid0" },
+ .csid = {
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .hw_ops = &csid_ops_gen3,
+ .formats = &csid_formats_gen2,
+ },
+ },
+ /* CSID1 */
+ {
+ .regulators = { },
+ .clock = { "csid", "csiphy_rx" },
+ .clock_rate = { { 400000000 },
+ { 400000000, 480000000 } },
+ .reg = { "csid1" },
+ .interrupt = { "csid1" },
+ .csid = {
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .hw_ops = &csid_ops_gen3,
+ .formats = &csid_formats_gen2,
+ },
+ },
+ /* CSID2 */
+ {
+ .regulators = { },
+ .clock = { "csid", "csiphy_rx" },
+ .clock_rate = { { 400000000 },
+ { 400000000, 480000000 } },
+ .reg = { "csid2" },
+ .interrupt = { "csid2" },
+ .csid = {
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .hw_ops = &csid_ops_gen3,
+ .formats = &csid_formats_gen2,
+ },
+ },
+ /* CSID3 lite */
+ {
+ .regulators = { },
+ .clock = { "vfe_lite_ahb", "vfe_lite_csid", "vfe_lite_cphy_rx" },
+ .clock_rate = { { 0 },
+ { 400000000, 480000000 },
+ { 0 } },
+ .reg = { "csid_lite0" },
+ .interrupt = { "csid_lite0" },
+ .csid = {
+ .is_lite = true,
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .hw_ops = &csid_ops_gen3,
+ .formats = &csid_formats_gen2,
+ },
+ },
+ /* CSID4 lite */
+ {
+ .regulators = { },
+ .clock = { "vfe_lite_ahb", "vfe_lite_csid", "vfe_lite_cphy_rx" },
+ .clock_rate = { { 0 },
+ { 400000000, 480000000 },
+ { 0 } },
+ .reg = { "csid_lite1" },
+ .interrupt = { "csid_lite1" },
+ .csid = {
+ .is_lite = true,
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .hw_ops = &csid_ops_gen3,
+ .formats = &csid_formats_gen2,
+ },
+ },
+};
+
+static const struct camss_subdev_resources vfe_res_sm8650[] = {
+ /* VFE0 */
+ {
+ .regulators = { },
+ .clock = { "gcc_axi_hf", "cpas_ahb", "cpas_fast_ahb",
+ "camnoc_axi", "vfe0_fast_ahb", "vfe0", "cpas_vfe0",
+ "qdss_debug_xo",
+ },
+ .clock_rate = { { 0 },
+ { 80000000 },
+ { 300000000, 400000000 },
+ { 300000000, 400000000 },
+ { 0 },
+ { 466000000, 594000000, 675000000, 785000000 },
+ { 0 },
+ { 0 },
+ },
+ .reg = { "vfe0" },
+ .interrupt = { "vfe0" },
+ .vfe = {
+ .line_num = 3,
+ .has_pd = true,
+ .pd_name = "ife0",
+ .hw_ops = &vfe_ops_gen3,
+ .formats_rdi = &vfe_formats_rdi_845,
+ .formats_pix = &vfe_formats_pix_845
+ },
+ },
+ /* VFE1 */
+ {
+ .regulators = { },
+ .clock = { "gcc_axi_hf", "cpas_ahb", "cpas_fast_ahb",
+ "camnoc_axi", "vfe1_fast_ahb", "vfe1", "cpas_vfe1",
+ "qdss_debug_xo",
+ },
+ .clock_rate = { { 0 },
+ { 80000000 },
+ { 300000000, 400000000 },
+ { 300000000, 400000000 },
+ { 0 },
+ { 466000000, 594000000, 675000000, 785000000 },
+ { 0 },
+ { 0 },
+ },
+ .reg = { "vfe1" },
+ .interrupt = { "vfe1" },
+ .vfe = {
+ .line_num = 3,
+ .has_pd = true,
+ .pd_name = "ife1",
+ .hw_ops = &vfe_ops_gen3,
+ .formats_rdi = &vfe_formats_rdi_845,
+ .formats_pix = &vfe_formats_pix_845
+ },
+ },
+ /* VFE2 */
+ {
+ .regulators = { },
+ .clock = { "gcc_axi_hf", "cpas_ahb", "cpas_fast_ahb",
+ "camnoc_axi", "vfe2_fast_ahb", "vfe2", "cpas_vfe2",
+ "qdss_debug_xo",
+ },
+ .clock_rate = { { 0 },
+ { 80000000 },
+ { 300000000, 400000000 },
+ { 300000000, 400000000 },
+ { 0 },
+ { 466000000, 594000000, 675000000, 785000000 },
+ { 0 },
+ { 0 },
+ },
+ .reg = { "vfe2" },
+ .interrupt = { "vfe2" },
+ .vfe = {
+ .line_num = 3,
+ .has_pd = true,
+ .pd_name = "ife2",
+ .hw_ops = &vfe_ops_gen3,
+ .formats_rdi = &vfe_formats_rdi_845,
+ .formats_pix = &vfe_formats_pix_845
+ },
+ },
+ /* VFE3 lite */
+ {
+ .regulators = { },
+ .clock = { "gcc_axi_hf", "cpas_ahb", "camnoc_axi",
+ "vfe_lite_ahb", "vfe_lite", "cpas_vfe_lite",
+ "qdss_debug_xo",
+ },
+ .clock_rate = { { 0 },
+ { 80000000 },
+ { 300000000, 400000000 },
+ { 0 },
+ { 400000000, 480000000 },
+ { 0 },
+ { 0 },
+ },
+ .reg = { "vfe_lite0" },
+ .interrupt = { "vfe_lite0" },
+ .vfe = {
+ .line_num = 4,
+ .is_lite = true,
+ .hw_ops = &vfe_ops_gen3,
+ .formats_rdi = &vfe_formats_rdi_845,
+ .formats_pix = &vfe_formats_pix_845
+ },
+ },
+ /* VFE4 lite */
+ {
+ .regulators = { },
+ .clock = { "gcc_axi_hf", "cpas_ahb", "camnoc_axi",
+ "vfe_lite_ahb", "vfe_lite", "cpas_vfe_lite",
+ "qdss_debug_xo",
+ },
+ .clock_rate = { { 0 },
+ { 80000000 },
+ { 300000000, 400000000 },
+ { 0 },
+ { 400000000, 480000000 },
+ { 0 },
+ { 0 },
+ },
+ .reg = { "vfe_lite1" },
+ .interrupt = { "vfe_lite1" },
+ .vfe = {
+ .line_num = 4,
+ .is_lite = true,
+ .hw_ops = &vfe_ops_gen3,
+ .formats_rdi = &vfe_formats_rdi_845,
+ .formats_pix = &vfe_formats_pix_845
+ },
+ },
+};
+
+static const struct resources_icc icc_res_sm8650[] = {
+ {
+ .name = "ahb",
+ .icc_bw_tbl.avg = 38400,
+ .icc_bw_tbl.peak = 76800,
+ },
+ {
+ .name = "hf_mnoc",
+ .icc_bw_tbl.avg = 2097152,
+ .icc_bw_tbl.peak = 2097152,
+ },
+};
+
static const struct camss_subdev_resources csiphy_res_8300[] = {
/* CSIPHY0 */
{
@@ -4452,6 +4763,20 @@ static const struct camss_resources sm8550_resources = {
.vfe_num = ARRAY_SIZE(vfe_res_8550),
};
+static const struct camss_resources sm8650_resources = {
+ .version = CAMSS_8650,
+ .pd_name = "top",
+ .csiphy_res = csiphy_res_sm8650,
+ .csid_res = csid_res_sm8650,
+ .csid_wrapper_res = &csid_wrapper_res_sm8550,
+ .vfe_res = vfe_res_sm8650,
+ .icc_res = icc_res_sm8650,
+ .icc_path_num = ARRAY_SIZE(icc_res_sm8650),
+ .csiphy_num = ARRAY_SIZE(csiphy_res_sm8650),
+ .csid_num = ARRAY_SIZE(csid_res_sm8650),
+ .vfe_num = ARRAY_SIZE(vfe_res_sm8650),
+};
+
static const struct camss_resources x1e80100_resources = {
.version = CAMSS_X1E80100,
.pd_name = "top",
@@ -4480,6 +4805,7 @@ static const struct of_device_id camss_dt_match[] = {
{ .compatible = "qcom,sdm845-camss", .data = &sdm845_resources },
{ .compatible = "qcom,sm8250-camss", .data = &sm8250_resources },
{ .compatible = "qcom,sm8550-camss", .data = &sm8550_resources },
+ { .compatible = "qcom,sm8650-camss", .data = &sm8650_resources },
{ .compatible = "qcom,x1e80100-camss", .data = &x1e80100_resources },
{ }
};
diff --git a/drivers/media/platform/qcom/camss/camss.h b/drivers/media/platform/qcom/camss/camss.h
index a70fbc78ccc3..1875f145995b 100644
--- a/drivers/media/platform/qcom/camss/camss.h
+++ b/drivers/media/platform/qcom/camss/camss.h
@@ -88,6 +88,7 @@ enum camss_version {
CAMSS_8300,
CAMSS_845,
CAMSS_8550,
+ CAMSS_8650,
CAMSS_8775P,
CAMSS_X1E80100,
};
--
2.49.0
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [PATCH v3 2/4] media: qcom: camss: Add Qualcomm SM8650 CAMSS support
2025-10-17 3:11 ` [PATCH v3 2/4] media: qcom: camss: Add Qualcomm SM8650 CAMSS support Vladimir Zapolskiy
@ 2025-10-23 15:10 ` Bryan O'Donoghue
0 siblings, 0 replies; 11+ messages in thread
From: Bryan O'Donoghue @ 2025-10-23 15:10 UTC (permalink / raw)
To: Vladimir Zapolskiy, Robert Foss, Todor Tomov,
Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Bjorn Andersson, Konrad Dybcio
Cc: Neil Armstrong, linux-arm-msm, linux-media, devicetree
On 17/10/2025 04:11, Vladimir Zapolskiy wrote:
> Add the basic support of CAMSS IP on Qualcomm SM8650 SoC powered boards.
>
> SM8650 CAMSS provides:
> - 6 x CSIPHY,
> - 3 x CSID, 2 x CSID Lite,
> - 3 x VFE, 2 x VFE Lite.
>
> Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
> ---
> drivers/media/platform/qcom/camss/camss-vfe.c | 2 +
> drivers/media/platform/qcom/camss/camss.c | 326 ++++++++++++++++++
> drivers/media/platform/qcom/camss/camss.h | 1 +
> 3 files changed, 329 insertions(+)
>
> diff --git a/drivers/media/platform/qcom/camss/camss-vfe.c b/drivers/media/platform/qcom/camss/camss-vfe.c
> index dff8d0a1e8c2..f76bcf69159a 100644
> --- a/drivers/media/platform/qcom/camss/camss-vfe.c
> +++ b/drivers/media/platform/qcom/camss/camss-vfe.c
> @@ -348,6 +348,7 @@ static u32 vfe_src_pad_code(struct vfe_line *line, u32 sink_code,
> case CAMSS_8300:
> case CAMSS_845:
> case CAMSS_8550:
> + case CAMSS_8650:
> case CAMSS_8775P:
> case CAMSS_X1E80100:
> switch (sink_code) {
> @@ -1995,6 +1996,7 @@ static int vfe_bpl_align(struct vfe_device *vfe)
> case CAMSS_8300:
> case CAMSS_845:
> case CAMSS_8550:
> + case CAMSS_8650:
> case CAMSS_8775P:
> case CAMSS_X1E80100:
> ret = 16;
> diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c
> index 2fbcd0e343aa..06a184fb9ae3 100644
> --- a/drivers/media/platform/qcom/camss/camss.c
> +++ b/drivers/media/platform/qcom/camss/camss.c
> @@ -2617,6 +2617,317 @@ static const struct resources_icc icc_res_sm8550[] = {
> },
> };
>
> +static const struct camss_subdev_resources csiphy_res_sm8650[] = {
> + /* CSIPHY0 */
> + {
> + .regulators = { "vdd-csiphy01-0p9", "vdd-csiphy01-1p2", },
> + .clock = { "csiphy0", "csiphy0_timer" },
> + .clock_rate = { { 400000000 },
> + { 400000000 } },
> + .reg = { "csiphy0" },
> + .interrupt = { "csiphy0" },
> + .csiphy = {
> + .id = 0,
> + .hw_ops = &csiphy_ops_3ph_1_0,
> + .formats = &csiphy_formats_sdm845,
> + },
> + },
> + /* CSIPHY1 */
> + {
> + .regulators = { "vdd-csiphy01-0p9", "vdd-csiphy01-1p2", },
> + .clock = { "csiphy1", "csiphy1_timer" },
> + .clock_rate = { { 400000000 },
> + { 400000000 } },
> + .reg = { "csiphy1" },
> + .interrupt = { "csiphy1" },
> + .csiphy = {
> + .id = 1,
> + .hw_ops = &csiphy_ops_3ph_1_0,
> + .formats = &csiphy_formats_sdm845,
> + },
> + },
> + /* CSIPHY2 */
> + {
> + .regulators = { "vdd-csiphy24-0p9", "vdd-csiphy24-1p2", },
> + .clock = { "csiphy2", "csiphy2_timer" },
> + .clock_rate = { { 400000000 },
> + { 400000000 } },
> + .reg = { "csiphy2" },
> + .interrupt = { "csiphy2" },
> + .csiphy = {
> + .id = 2,
> + .hw_ops = &csiphy_ops_3ph_1_0,
> + .formats = &csiphy_formats_sdm845,
> + },
> + },
> + /* CSIPHY3 */
> + {
> + .regulators = { "vdd-csiphy35-0p9", "vdd-csiphy35-1p2", },
> + .clock = { "csiphy3", "csiphy3_timer" },
> + .clock_rate = { { 400000000 },
> + { 400000000 } },
> + .reg = { "csiphy3" },
> + .interrupt = { "csiphy3" },
> + .csiphy = {
> + .id = 3,
> + .hw_ops = &csiphy_ops_3ph_1_0,
> + .formats = &csiphy_formats_sdm845,
> + },
> + },
> + /* CSIPHY4 */
> + {
> + .regulators = { "vdd-csiphy24-0p9", "vdd-csiphy24-1p2", },
> + .clock = { "csiphy4", "csiphy4_timer" },
> + .clock_rate = { { 400000000 },
> + { 400000000 } },
> + .reg = { "csiphy4" },
> + .interrupt = { "csiphy4" },
> + .csiphy = {
> + .id = 4,
> + .hw_ops = &csiphy_ops_3ph_1_0,
> + .formats = &csiphy_formats_sdm845,
> + },
> + },
> + /* CSIPHY5 */
> + {
> + .regulators = { "vdd-csiphy35-0p9", "vdd-csiphy35-1p2", },
> + .clock = { "csiphy5", "csiphy5_timer" },
> + .clock_rate = { { 400000000 },
> + { 400000000 } },
> + .reg = { "csiphy5" },
> + .interrupt = { "csiphy5" },
> + .csiphy = {
> + .id = 5,
> + .hw_ops = &csiphy_ops_3ph_1_0,
> + .formats = &csiphy_formats_sdm845,
> + },
> + },
> +};
> +
> +static const struct camss_subdev_resources csid_res_sm8650[] = {
> + /* CSID0 */
> + {
> + .regulators = { },
> + .clock = { "csid", "csiphy_rx" },
> + .clock_rate = { { 400000000 },
> + { 400000000, 480000000 } },
> + .reg = { "csid0" },
> + .interrupt = { "csid0" },
> + .csid = {
> + .parent_dev_ops = &vfe_parent_dev_ops,
> + .hw_ops = &csid_ops_gen3,
> + .formats = &csid_formats_gen2,
> + },
> + },
> + /* CSID1 */
> + {
> + .regulators = { },
> + .clock = { "csid", "csiphy_rx" },
> + .clock_rate = { { 400000000 },
> + { 400000000, 480000000 } },
> + .reg = { "csid1" },
> + .interrupt = { "csid1" },
> + .csid = {
> + .parent_dev_ops = &vfe_parent_dev_ops,
> + .hw_ops = &csid_ops_gen3,
> + .formats = &csid_formats_gen2,
> + },
> + },
> + /* CSID2 */
> + {
> + .regulators = { },
> + .clock = { "csid", "csiphy_rx" },
> + .clock_rate = { { 400000000 },
> + { 400000000, 480000000 } },
> + .reg = { "csid2" },
> + .interrupt = { "csid2" },
> + .csid = {
> + .parent_dev_ops = &vfe_parent_dev_ops,
> + .hw_ops = &csid_ops_gen3,
> + .formats = &csid_formats_gen2,
> + },
> + },
> + /* CSID3 lite */
> + {
> + .regulators = { },
> + .clock = { "vfe_lite_ahb", "vfe_lite_csid", "vfe_lite_cphy_rx" },
> + .clock_rate = { { 0 },
> + { 400000000, 480000000 },
> + { 0 } },
> + .reg = { "csid_lite0" },
> + .interrupt = { "csid_lite0" },
> + .csid = {
> + .is_lite = true,
> + .parent_dev_ops = &vfe_parent_dev_ops,
> + .hw_ops = &csid_ops_gen3,
> + .formats = &csid_formats_gen2,
> + },
> + },
> + /* CSID4 lite */
> + {
> + .regulators = { },
> + .clock = { "vfe_lite_ahb", "vfe_lite_csid", "vfe_lite_cphy_rx" },
> + .clock_rate = { { 0 },
> + { 400000000, 480000000 },
> + { 0 } },
> + .reg = { "csid_lite1" },
> + .interrupt = { "csid_lite1" },
> + .csid = {
> + .is_lite = true,
> + .parent_dev_ops = &vfe_parent_dev_ops,
> + .hw_ops = &csid_ops_gen3,
> + .formats = &csid_formats_gen2,
> + },
> + },
> +};
> +
> +static const struct camss_subdev_resources vfe_res_sm8650[] = {
> + /* VFE0 */
> + {
> + .regulators = { },
> + .clock = { "gcc_axi_hf", "cpas_ahb", "cpas_fast_ahb",
> + "camnoc_axi", "vfe0_fast_ahb", "vfe0", "cpas_vfe0",
> + "qdss_debug_xo",
> + },
> + .clock_rate = { { 0 },
> + { 80000000 },
> + { 300000000, 400000000 },
> + { 300000000, 400000000 },
> + { 0 },
> + { 466000000, 594000000, 675000000, 785000000 },
> + { 0 },
> + { 0 },
> + },
> + .reg = { "vfe0" },
> + .interrupt = { "vfe0" },
> + .vfe = {
> + .line_num = 3,
> + .has_pd = true,
> + .pd_name = "ife0",
> + .hw_ops = &vfe_ops_gen3,
> + .formats_rdi = &vfe_formats_rdi_845,
> + .formats_pix = &vfe_formats_pix_845
> + },
> + },
> + /* VFE1 */
> + {
> + .regulators = { },
> + .clock = { "gcc_axi_hf", "cpas_ahb", "cpas_fast_ahb",
> + "camnoc_axi", "vfe1_fast_ahb", "vfe1", "cpas_vfe1",
> + "qdss_debug_xo",
> + },
> + .clock_rate = { { 0 },
> + { 80000000 },
> + { 300000000, 400000000 },
> + { 300000000, 400000000 },
> + { 0 },
> + { 466000000, 594000000, 675000000, 785000000 },
> + { 0 },
> + { 0 },
> + },
> + .reg = { "vfe1" },
> + .interrupt = { "vfe1" },
> + .vfe = {
> + .line_num = 3,
> + .has_pd = true,
> + .pd_name = "ife1",
> + .hw_ops = &vfe_ops_gen3,
> + .formats_rdi = &vfe_formats_rdi_845,
> + .formats_pix = &vfe_formats_pix_845
> + },
> + },
> + /* VFE2 */
> + {
> + .regulators = { },
> + .clock = { "gcc_axi_hf", "cpas_ahb", "cpas_fast_ahb",
> + "camnoc_axi", "vfe2_fast_ahb", "vfe2", "cpas_vfe2",
> + "qdss_debug_xo",
> + },
> + .clock_rate = { { 0 },
> + { 80000000 },
> + { 300000000, 400000000 },
> + { 300000000, 400000000 },
> + { 0 },
> + { 466000000, 594000000, 675000000, 785000000 },
> + { 0 },
> + { 0 },
> + },
> + .reg = { "vfe2" },
> + .interrupt = { "vfe2" },
> + .vfe = {
> + .line_num = 3,
> + .has_pd = true,
> + .pd_name = "ife2",
> + .hw_ops = &vfe_ops_gen3,
> + .formats_rdi = &vfe_formats_rdi_845,
> + .formats_pix = &vfe_formats_pix_845
> + },
> + },
> + /* VFE3 lite */
> + {
> + .regulators = { },
> + .clock = { "gcc_axi_hf", "cpas_ahb", "camnoc_axi",
> + "vfe_lite_ahb", "vfe_lite", "cpas_vfe_lite",
> + "qdss_debug_xo",
> + },
> + .clock_rate = { { 0 },
> + { 80000000 },
> + { 300000000, 400000000 },
> + { 0 },
> + { 400000000, 480000000 },
> + { 0 },
> + { 0 },
> + },
> + .reg = { "vfe_lite0" },
> + .interrupt = { "vfe_lite0" },
> + .vfe = {
> + .line_num = 4,
> + .is_lite = true,
> + .hw_ops = &vfe_ops_gen3,
> + .formats_rdi = &vfe_formats_rdi_845,
> + .formats_pix = &vfe_formats_pix_845
> + },
> + },
> + /* VFE4 lite */
> + {
> + .regulators = { },
> + .clock = { "gcc_axi_hf", "cpas_ahb", "camnoc_axi",
> + "vfe_lite_ahb", "vfe_lite", "cpas_vfe_lite",
> + "qdss_debug_xo",
> + },
> + .clock_rate = { { 0 },
> + { 80000000 },
> + { 300000000, 400000000 },
> + { 0 },
> + { 400000000, 480000000 },
> + { 0 },
> + { 0 },
> + },
> + .reg = { "vfe_lite1" },
> + .interrupt = { "vfe_lite1" },
> + .vfe = {
> + .line_num = 4,
> + .is_lite = true,
> + .hw_ops = &vfe_ops_gen3,
> + .formats_rdi = &vfe_formats_rdi_845,
> + .formats_pix = &vfe_formats_pix_845
> + },
> + },
> +};
> +
> +static const struct resources_icc icc_res_sm8650[] = {
> + {
> + .name = "ahb",
> + .icc_bw_tbl.avg = 38400,
> + .icc_bw_tbl.peak = 76800,
> + },
> + {
> + .name = "hf_mnoc",
> + .icc_bw_tbl.avg = 2097152,
This value looks dubious.
Not worth holding up the set for though.
> + .icc_bw_tbl.peak = 2097152,
> + },
> +};
> +
> static const struct camss_subdev_resources csiphy_res_8300[] = {
> /* CSIPHY0 */
> {
> @@ -4452,6 +4763,20 @@ static const struct camss_resources sm8550_resources = {
> .vfe_num = ARRAY_SIZE(vfe_res_8550),
> };
>
> +static const struct camss_resources sm8650_resources = {
> + .version = CAMSS_8650,
> + .pd_name = "top",
> + .csiphy_res = csiphy_res_sm8650,
> + .csid_res = csid_res_sm8650,
> + .csid_wrapper_res = &csid_wrapper_res_sm8550,
> + .vfe_res = vfe_res_sm8650,
> + .icc_res = icc_res_sm8650,
> + .icc_path_num = ARRAY_SIZE(icc_res_sm8650),
> + .csiphy_num = ARRAY_SIZE(csiphy_res_sm8650),
> + .csid_num = ARRAY_SIZE(csid_res_sm8650),
> + .vfe_num = ARRAY_SIZE(vfe_res_sm8650),
> +};
> +
> static const struct camss_resources x1e80100_resources = {
> .version = CAMSS_X1E80100,
> .pd_name = "top",
> @@ -4480,6 +4805,7 @@ static const struct of_device_id camss_dt_match[] = {
> { .compatible = "qcom,sdm845-camss", .data = &sdm845_resources },
> { .compatible = "qcom,sm8250-camss", .data = &sm8250_resources },
> { .compatible = "qcom,sm8550-camss", .data = &sm8550_resources },
> + { .compatible = "qcom,sm8650-camss", .data = &sm8650_resources },
> { .compatible = "qcom,x1e80100-camss", .data = &x1e80100_resources },
> { }
> };
> diff --git a/drivers/media/platform/qcom/camss/camss.h b/drivers/media/platform/qcom/camss/camss.h
> index a70fbc78ccc3..1875f145995b 100644
> --- a/drivers/media/platform/qcom/camss/camss.h
> +++ b/drivers/media/platform/qcom/camss/camss.h
> @@ -88,6 +88,7 @@ enum camss_version {
> CAMSS_8300,
> CAMSS_845,
> CAMSS_8550,
> + CAMSS_8650,
> CAMSS_8775P,
> CAMSS_X1E80100,
> };
> --
> 2.49.0
>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v3 3/4] media: qcom: camss: Add CSIPHY 2.2.0 lane configuration for SM8650
2025-10-17 3:11 [PATCH v3 0/4] media: qcom: camss: Add Qualcomm SM8650 CAMSS support Vladimir Zapolskiy
2025-10-17 3:11 ` [PATCH v3 1/4] dt-bindings: media: Describe Qualcomm SM8650 CAMSS IP Vladimir Zapolskiy
2025-10-17 3:11 ` [PATCH v3 2/4] media: qcom: camss: Add Qualcomm SM8650 CAMSS support Vladimir Zapolskiy
@ 2025-10-17 3:11 ` Vladimir Zapolskiy
2025-10-23 15:15 ` Bryan O'Donoghue
2025-10-17 3:11 ` [PATCH v3 4/4] arm64: dts: qcom: sm8650: Add CAMSS device tree node Vladimir Zapolskiy
2025-10-23 15:52 ` [PATCH v3 0/4] media: qcom: camss: Add Qualcomm SM8650 CAMSS support Neil Armstrong
4 siblings, 1 reply; 11+ messages in thread
From: Vladimir Zapolskiy @ 2025-10-17 3:11 UTC (permalink / raw)
To: Bryan O'Donoghue, Robert Foss, Todor Tomov,
Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Bjorn Andersson, Konrad Dybcio
Cc: Neil Armstrong, linux-arm-msm, linux-media, devicetree
Add a configuration for all CSI lanes into D-PHY bus mode on Qualcomm
SM8650 CAMSS CSIPHY IPs.
Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
---
.../qcom/camss/camss-csiphy-3ph-1-0.c | 102 ++++++++++++++++++
1 file changed, 102 insertions(+)
diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
index a229ba04b158..619abbf60781 100644
--- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
+++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
@@ -587,6 +587,102 @@ csiphy_lane_regs lane_regs_sm8550[] = {
{0x0C64, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
};
+/* GEN2 2.2.0 2PH 4 lane DPHY mode */
+static const struct
+csiphy_lane_regs lane_regs_sm8650[] = {
+ {0x0e94, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0ea0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0e90, 0x0f, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0e98, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0e94, 0x07, 0xd1, CSIPHY_DEFAULT_PARAMS},
+ {0x0e30, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0e28, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0e00, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0e0c, 0xff, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0e38, 0x1f, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0e2c, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0e34, 0x0f, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0e1c, 0x0a, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0e14, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0e3c, 0xb8, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0e04, 0x0c, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0e20, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0e08, 0x19, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
+ {0x0e10, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
+
+ {0x0094, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x00a0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0090, 0x0f, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0098, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0094, 0x07, 0xd1, CSIPHY_DEFAULT_PARAMS},
+ {0x0030, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0000, 0x8e, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0038, 0xfe, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x002c, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0034, 0x0f, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x001c, 0x0a, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0014, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x003c, 0xb8, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0004, 0x0c, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0020, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0008, 0x19, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
+ {0x0010, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
+
+ {0x0494, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x04a0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0490, 0x0f, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0498, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0494, 0x07, 0xd1, CSIPHY_DEFAULT_PARAMS},
+ {0x0430, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0400, 0x8e, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0438, 0xfe, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x042c, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0434, 0x0f, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x041c, 0x0a, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0414, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x043c, 0xb8, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0404, 0x0c, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0420, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0408, 0x19, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
+ {0x0410, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
+
+ {0x0894, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x08a0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0890, 0x0f, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0898, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0894, 0x07, 0xd1, CSIPHY_DEFAULT_PARAMS},
+ {0x0830, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0800, 0x8e, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0838, 0xfe, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x082c, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0834, 0x0f, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x081c, 0x0a, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0814, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x083c, 0xb8, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0804, 0x0c, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0820, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0808, 0x19, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
+ {0x0810, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
+
+ {0x0c94, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0ca0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0c90, 0x0f, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0c98, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0c94, 0x07, 0xd1, CSIPHY_DEFAULT_PARAMS},
+ {0x0c30, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0c00, 0x8e, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0c38, 0xfe, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0c2c, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0c34, 0x0f, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0c1c, 0x0a, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0c14, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0c3c, 0xb8, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0c04, 0x0c, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0c20, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0c08, 0x19, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
+ {0x0c10, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
+};
+
/* 4nm 2PH v 2.1.2 2p5Gbps 4 lane DPHY mode */
static const struct
csiphy_lane_regs lane_regs_x1e80100[] = {
@@ -914,6 +1010,7 @@ static bool csiphy_is_gen2(u32 version)
case CAMSS_8300:
case CAMSS_845:
case CAMSS_8550:
+ case CAMSS_8650:
case CAMSS_8775P:
case CAMSS_X1E80100:
ret = true;
@@ -1018,6 +1115,11 @@ static int csiphy_init(struct csiphy_device *csiphy)
regs->lane_array_size = ARRAY_SIZE(lane_regs_sm8550);
regs->offset = 0x1000;
break;
+ case CAMSS_8650:
+ regs->lane_regs = &lane_regs_sm8650[0];
+ regs->lane_array_size = ARRAY_SIZE(lane_regs_sm8650);
+ regs->offset = 0x1000;
+ break;
case CAMSS_8300:
case CAMSS_8775P:
regs->lane_regs = &lane_regs_sa8775p[0];
--
2.49.0
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [PATCH v3 3/4] media: qcom: camss: Add CSIPHY 2.2.0 lane configuration for SM8650
2025-10-17 3:11 ` [PATCH v3 3/4] media: qcom: camss: Add CSIPHY 2.2.0 lane configuration for SM8650 Vladimir Zapolskiy
@ 2025-10-23 15:15 ` Bryan O'Donoghue
0 siblings, 0 replies; 11+ messages in thread
From: Bryan O'Donoghue @ 2025-10-23 15:15 UTC (permalink / raw)
To: Vladimir Zapolskiy, Robert Foss, Todor Tomov,
Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Bjorn Andersson, Konrad Dybcio
Cc: Neil Armstrong, linux-arm-msm, linux-media, devicetree
On 17/10/2025 04:11, Vladimir Zapolskiy wrote:
> Add a configuration for all CSI lanes into D-PHY bus mode on Qualcomm
> SM8650 CAMSS CSIPHY IPs.
>
> Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
> ---
> .../qcom/camss/camss-csiphy-3ph-1-0.c | 102 ++++++++++++++++++
> 1 file changed, 102 insertions(+)
>
> diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
> index a229ba04b158..619abbf60781 100644
> --- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
> +++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
> @@ -587,6 +587,102 @@ csiphy_lane_regs lane_regs_sm8550[] = {
> {0x0C64, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
> };
>
> +/* GEN2 2.2.0 2PH 4 lane DPHY mode */
> +static const struct
> +csiphy_lane_regs lane_regs_sm8650[] = {
> + {0x0e94, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0ea0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0e90, 0x0f, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0e98, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0e94, 0x07, 0xd1, CSIPHY_DEFAULT_PARAMS},
> + {0x0e30, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0e28, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0e00, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0e0c, 0xff, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0e38, 0x1f, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0e2c, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0e34, 0x0f, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0e1c, 0x0a, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0e14, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0e3c, 0xb8, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0e04, 0x0c, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0e20, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0e08, 0x19, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
> + {0x0e10, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
> +
> + {0x0094, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x00a0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0090, 0x0f, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0098, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0094, 0x07, 0xd1, CSIPHY_DEFAULT_PARAMS},
> + {0x0030, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0000, 0x8e, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0038, 0xfe, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x002c, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0034, 0x0f, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x001c, 0x0a, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0014, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x003c, 0xb8, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0004, 0x0c, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0020, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0008, 0x19, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
> + {0x0010, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
> +
> + {0x0494, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x04a0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0490, 0x0f, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0498, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0494, 0x07, 0xd1, CSIPHY_DEFAULT_PARAMS},
> + {0x0430, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0400, 0x8e, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0438, 0xfe, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x042c, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0434, 0x0f, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x041c, 0x0a, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0414, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x043c, 0xb8, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0404, 0x0c, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0420, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0408, 0x19, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
> + {0x0410, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
> +
> + {0x0894, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x08a0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0890, 0x0f, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0898, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0894, 0x07, 0xd1, CSIPHY_DEFAULT_PARAMS},
> + {0x0830, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0800, 0x8e, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0838, 0xfe, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x082c, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0834, 0x0f, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x081c, 0x0a, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0814, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x083c, 0xb8, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0804, 0x0c, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0820, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0808, 0x19, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
> + {0x0810, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
> +
> + {0x0c94, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0ca0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0c90, 0x0f, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0c98, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0c94, 0x07, 0xd1, CSIPHY_DEFAULT_PARAMS},
> + {0x0c30, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0c00, 0x8e, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0c38, 0xfe, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0c2c, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0c34, 0x0f, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0c1c, 0x0a, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0c14, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0c3c, 0xb8, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0c04, 0x0c, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0c20, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0c08, 0x19, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
> + {0x0c10, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
> +};
> +
> /* 4nm 2PH v 2.1.2 2p5Gbps 4 lane DPHY mode */
> static const struct
> csiphy_lane_regs lane_regs_x1e80100[] = {
> @@ -914,6 +1010,7 @@ static bool csiphy_is_gen2(u32 version)
> case CAMSS_8300:
> case CAMSS_845:
> case CAMSS_8550:
> + case CAMSS_8650:
> case CAMSS_8775P:
> case CAMSS_X1E80100:
> ret = true;
> @@ -1018,6 +1115,11 @@ static int csiphy_init(struct csiphy_device *csiphy)
> regs->lane_array_size = ARRAY_SIZE(lane_regs_sm8550);
> regs->offset = 0x1000;
> break;
> + case CAMSS_8650:
> + regs->lane_regs = &lane_regs_sm8650[0];
> + regs->lane_array_size = ARRAY_SIZE(lane_regs_sm8650);
> + regs->offset = 0x1000;
> + break;
> case CAMSS_8300:
> case CAMSS_8775P:
> regs->lane_regs = &lane_regs_sa8775p[0];
> --
> 2.49.0
>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v3 4/4] arm64: dts: qcom: sm8650: Add CAMSS device tree node
2025-10-17 3:11 [PATCH v3 0/4] media: qcom: camss: Add Qualcomm SM8650 CAMSS support Vladimir Zapolskiy
` (2 preceding siblings ...)
2025-10-17 3:11 ` [PATCH v3 3/4] media: qcom: camss: Add CSIPHY 2.2.0 lane configuration for SM8650 Vladimir Zapolskiy
@ 2025-10-17 3:11 ` Vladimir Zapolskiy
2025-10-23 15:17 ` Bryan O'Donoghue
2025-10-23 15:52 ` [PATCH v3 0/4] media: qcom: camss: Add Qualcomm SM8650 CAMSS support Neil Armstrong
4 siblings, 1 reply; 11+ messages in thread
From: Vladimir Zapolskiy @ 2025-10-17 3:11 UTC (permalink / raw)
To: Bryan O'Donoghue, Robert Foss, Todor Tomov,
Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Bjorn Andersson, Konrad Dybcio
Cc: Neil Armstrong, linux-arm-msm, linux-media, devicetree
Add Qualcomm SM8650 CAMSS device tree node to the platform dtsi file,
the SM8650 CAMSS IP contains
* 6 x CSIPHY,
* 3 x CSID, 2 x CSID Lite,
* 3 x IFE, 2 x IFE Lite.
Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
---
arch/arm64/boot/dts/qcom/sm8650.dtsi | 180 +++++++++++++++++++++++++++
1 file changed, 180 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi
index ebf1971b1bfb..555305c1c70d 100644
--- a/arch/arm64/boot/dts/qcom/sm8650.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi
@@ -5343,6 +5343,186 @@ cci2_i2c1: i2c-bus@1 {
};
};
+ camss: isp@acb6000 {
+ compatible = "qcom,sm8650-camss";
+ reg = <0 0x0acb6000 0 0x1000>,
+ <0 0x0acb8000 0 0x1000>,
+ <0 0x0acba000 0 0x1000>,
+ <0 0x0acbc000 0 0x1000>,
+ <0 0x0accb000 0 0x1000>,
+ <0 0x0acd0000 0 0x1000>,
+ <0 0x0ace4000 0 0x2000>,
+ <0 0x0ace6000 0 0x2000>,
+ <0 0x0ace8000 0 0x2000>,
+ <0 0x0acea000 0 0x2000>,
+ <0 0x0acec000 0 0x2000>,
+ <0 0x0acee000 0 0x2000>,
+ <0 0x0ac62000 0 0xf000>,
+ <0 0x0ac71000 0 0xf000>,
+ <0 0x0ac80000 0 0xf000>,
+ <0 0x0accc000 0 0x2000>,
+ <0 0x0acd1000 0 0x2000>;
+ reg-names = "csid_wrapper",
+ "csid0",
+ "csid1",
+ "csid2",
+ "csid_lite0",
+ "csid_lite1",
+ "csiphy0",
+ "csiphy1",
+ "csiphy2",
+ "csiphy3",
+ "csiphy4",
+ "csiphy5",
+ "vfe0",
+ "vfe1",
+ "vfe2",
+ "vfe_lite0",
+ "vfe_lite1";
+ clocks = <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>,
+ <&camcc CAM_CC_CPAS_AHB_CLK>,
+ <&camcc CAM_CC_CPAS_FAST_AHB_CLK>,
+ <&camcc CAM_CC_CPAS_IFE_0_CLK>,
+ <&camcc CAM_CC_CPAS_IFE_1_CLK>,
+ <&camcc CAM_CC_CPAS_IFE_2_CLK>,
+ <&camcc CAM_CC_CPAS_IFE_LITE_CLK>,
+ <&camcc CAM_CC_CSID_CLK>,
+ <&camcc CAM_CC_CSIPHY0_CLK>,
+ <&camcc CAM_CC_CSI0PHYTIMER_CLK>,
+ <&camcc CAM_CC_CSI1PHYTIMER_CLK>,
+ <&camcc CAM_CC_CSIPHY1_CLK>,
+ <&camcc CAM_CC_CSI2PHYTIMER_CLK>,
+ <&camcc CAM_CC_CSIPHY2_CLK>,
+ <&camcc CAM_CC_CSI3PHYTIMER_CLK>,
+ <&camcc CAM_CC_CSIPHY3_CLK>,
+ <&camcc CAM_CC_CSI4PHYTIMER_CLK>,
+ <&camcc CAM_CC_CSIPHY4_CLK>,
+ <&camcc CAM_CC_CSI5PHYTIMER_CLK>,
+ <&camcc CAM_CC_CSIPHY5_CLK>,
+ <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>,
+ <&gcc GCC_CAMERA_HF_AXI_CLK>,
+ <&camcc CAM_CC_QDSS_DEBUG_XO_CLK>,
+ <&camcc CAM_CC_IFE_0_CLK>,
+ <&camcc CAM_CC_IFE_0_FAST_AHB_CLK>,
+ <&camcc CAM_CC_IFE_1_CLK>,
+ <&camcc CAM_CC_IFE_1_FAST_AHB_CLK>,
+ <&camcc CAM_CC_IFE_2_CLK>,
+ <&camcc CAM_CC_IFE_2_FAST_AHB_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CLK>,
+ <&camcc CAM_CC_IFE_LITE_AHB_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CSID_CLK>;
+ clock-names = "camnoc_axi",
+ "cpas_ahb",
+ "cpas_fast_ahb",
+ "cpas_vfe0",
+ "cpas_vfe1",
+ "cpas_vfe2",
+ "cpas_vfe_lite",
+ "csid",
+ "csiphy0",
+ "csiphy0_timer",
+ "csiphy1",
+ "csiphy1_timer",
+ "csiphy2",
+ "csiphy2_timer",
+ "csiphy3",
+ "csiphy3_timer",
+ "csiphy4",
+ "csiphy4_timer",
+ "csiphy5",
+ "csiphy5_timer",
+ "csiphy_rx",
+ "gcc_axi_hf",
+ "qdss_debug_xo",
+ "vfe0",
+ "vfe0_fast_ahb",
+ "vfe1",
+ "vfe1_fast_ahb",
+ "vfe2",
+ "vfe2_fast_ahb",
+ "vfe_lite",
+ "vfe_lite_ahb",
+ "vfe_lite_cphy_rx",
+ "vfe_lite_csid";
+ interrupts = <GIC_SPI 601 IRQ_TYPE_EDGE_RISING 0>,
+ <GIC_SPI 603 IRQ_TYPE_EDGE_RISING 0>,
+ <GIC_SPI 431 IRQ_TYPE_EDGE_RISING 0>,
+ <GIC_SPI 605 IRQ_TYPE_EDGE_RISING 0>,
+ <GIC_SPI 376 IRQ_TYPE_EDGE_RISING 0>,
+ <GIC_SPI 477 IRQ_TYPE_EDGE_RISING 0>,
+ <GIC_SPI 478 IRQ_TYPE_EDGE_RISING 0>,
+ <GIC_SPI 479 IRQ_TYPE_EDGE_RISING 0>,
+ <GIC_SPI 448 IRQ_TYPE_EDGE_RISING 0>,
+ <GIC_SPI 122 IRQ_TYPE_EDGE_RISING 0>,
+ <GIC_SPI 89 IRQ_TYPE_EDGE_RISING 0>,
+ <GIC_SPI 602 IRQ_TYPE_EDGE_RISING 0>,
+ <GIC_SPI 604 IRQ_TYPE_EDGE_RISING 0>,
+ <GIC_SPI 688 IRQ_TYPE_EDGE_RISING 0>,
+ <GIC_SPI 606 IRQ_TYPE_EDGE_RISING 0>,
+ <GIC_SPI 377 IRQ_TYPE_EDGE_RISING 0>;
+ interrupt-names = "csid0",
+ "csid1",
+ "csid2",
+ "csid_lite0",
+ "csid_lite1",
+ "csiphy0",
+ "csiphy1",
+ "csiphy2",
+ "csiphy3",
+ "csiphy4",
+ "csiphy5",
+ "vfe0",
+ "vfe1",
+ "vfe2",
+ "vfe_lite0",
+ "vfe_lite1";
+ interconnects = <&gem_noc MASTER_APPSS_PROC 0
+ &config_noc SLAVE_CAMERA_CFG 0>,
+ <&mmss_noc MASTER_CAMNOC_HF 0
+ &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "ahb",
+ "hf_mnoc";
+ iommus = <&apps_smmu 0x800 0x20>,
+ <&apps_smmu 0x18a0 0x40>,
+ <&apps_smmu 0x1860 0x00>;
+ power-domains = <&camcc CAM_CC_IFE_0_GDSC>,
+ <&camcc CAM_CC_IFE_1_GDSC>,
+ <&camcc CAM_CC_IFE_2_GDSC>,
+ <&camcc CAM_CC_TITAN_TOP_GDSC>;
+ power-domain-names = "ife0", "ife1", "ife2", "top";
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ };
+
+ port@1 {
+ reg = <1>;
+ };
+
+ port@2 {
+ reg = <2>;
+ };
+
+ port@3 {
+ reg = <3>;
+ };
+
+ port@4 {
+ reg = <4>;
+ };
+
+ port@5 {
+ reg = <5>;
+ };
+ };
+ };
+
camcc: clock-controller@ade0000 {
compatible = "qcom,sm8650-camcc";
reg = <0 0x0ade0000 0 0x20000>;
--
2.49.0
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [PATCH v3 4/4] arm64: dts: qcom: sm8650: Add CAMSS device tree node
2025-10-17 3:11 ` [PATCH v3 4/4] arm64: dts: qcom: sm8650: Add CAMSS device tree node Vladimir Zapolskiy
@ 2025-10-23 15:17 ` Bryan O'Donoghue
0 siblings, 0 replies; 11+ messages in thread
From: Bryan O'Donoghue @ 2025-10-23 15:17 UTC (permalink / raw)
To: Vladimir Zapolskiy, Robert Foss, Todor Tomov,
Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Bjorn Andersson, Konrad Dybcio
Cc: Neil Armstrong, linux-arm-msm, linux-media, devicetree
On 17/10/2025 04:11, Vladimir Zapolskiy wrote:
> Add Qualcomm SM8650 CAMSS device tree node to the platform dtsi file,
> the SM8650 CAMSS IP contains
> * 6 x CSIPHY,
> * 3 x CSID, 2 x CSID Lite,
> * 3 x IFE, 2 x IFE Lite.
>
> Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
> ---
> arch/arm64/boot/dts/qcom/sm8650.dtsi | 180 +++++++++++++++++++++++++++
> 1 file changed, 180 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi
> index ebf1971b1bfb..555305c1c70d 100644
> --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi
> @@ -5343,6 +5343,186 @@ cci2_i2c1: i2c-bus@1 {
> };
> };
>
> + camss: isp@acb6000 {
> + compatible = "qcom,sm8650-camss";
> + reg = <0 0x0acb6000 0 0x1000>,
> + <0 0x0acb8000 0 0x1000>,
> + <0 0x0acba000 0 0x1000>,
> + <0 0x0acbc000 0 0x1000>,
> + <0 0x0accb000 0 0x1000>,
> + <0 0x0acd0000 0 0x1000>,
> + <0 0x0ace4000 0 0x2000>,
> + <0 0x0ace6000 0 0x2000>,
> + <0 0x0ace8000 0 0x2000>,
> + <0 0x0acea000 0 0x2000>,
> + <0 0x0acec000 0 0x2000>,
> + <0 0x0acee000 0 0x2000>,
> + <0 0x0ac62000 0 0xf000>,
> + <0 0x0ac71000 0 0xf000>,
> + <0 0x0ac80000 0 0xf000>,
> + <0 0x0accc000 0 0x2000>,
> + <0 0x0acd1000 0 0x2000>;
> + reg-names = "csid_wrapper",
> + "csid0",
> + "csid1",
> + "csid2",
> + "csid_lite0",
> + "csid_lite1",
> + "csiphy0",
> + "csiphy1",
> + "csiphy2",
> + "csiphy3",
> + "csiphy4",
> + "csiphy5",
> + "vfe0",
> + "vfe1",
> + "vfe2",
> + "vfe_lite0",
> + "vfe_lite1";
So I don't believe the squashing down of node - subtracting newlines is
consistent with other entries in this dtsi.
It doesn't matter in the example but, here it should be consistent with
other nodes already here.
Think it should be updated/changed to match the rest.
---
bod
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v3 0/4] media: qcom: camss: Add Qualcomm SM8650 CAMSS support
2025-10-17 3:11 [PATCH v3 0/4] media: qcom: camss: Add Qualcomm SM8650 CAMSS support Vladimir Zapolskiy
` (3 preceding siblings ...)
2025-10-17 3:11 ` [PATCH v3 4/4] arm64: dts: qcom: sm8650: Add CAMSS device tree node Vladimir Zapolskiy
@ 2025-10-23 15:52 ` Neil Armstrong
4 siblings, 0 replies; 11+ messages in thread
From: Neil Armstrong @ 2025-10-23 15:52 UTC (permalink / raw)
To: Vladimir Zapolskiy, Bryan O'Donoghue, Robert Foss,
Todor Tomov, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson, Konrad Dybcio
Cc: linux-arm-msm, linux-media, devicetree
On 10/17/25 05:11, Vladimir Zapolskiy wrote:
> The Qualcomm SM8650 SoC contains a camera subsystem IP, which is
> got supported in the platform device tree by this change series.
>
> Qualcomm SM8650 CAMSS contains:
> * 6 x CSIPHY,
> * 3 x CSID, 2 x CSID Lite,
> * 3 x IFE, 2 x IFE Lite.
>
> Previously there was a version of SM8650 CAMSS dt bindings only sent for
> review, but it did not get any reviews from MSM or DT maintainers, this
> series is a fresh respin, and it includes the driver specific changes.
>
> The CAMSS changes were tested on SM8650-HDK and SM8650-QRD boards
> and SM5JN1 image sensor.
>
> Link to v2 version of the SM8650 CAMSS dt bindings changeset:
> - https://lore.kernel.org/linux-media/20250423221954.1926453-1-vladimir.zapolskiy@linaro.org/
>
> Changes from v2 to v3:
> * dropped excessive clock resourses,
> * dropped MCLK dts changes from the series, it will be added along
> with board specific changes,
> * the suggested comment to squash supply properties is not considered, since
> CSIPHYs on SM8650 boards have different supplies to different CSIPHYs,
> * added a CAMSS driver change and CSIPHY configuration specific to SM8650,
> * rebased on top of v6.18-rc1
>
> Link to v1 version of the changeset:
> - https://lore.kernel.org/linux-media/20250312001132.1832655-1-vladimir.zapolskiy@linaro.org
>
> Changes from v1 to v2:
> * to support a regex in port property names replaced 'properties' with
> 'patternProperties', a sanity check shall pass now, thanks to Dmitry,
> * added a few new line separators between property groups in sm8650.dtsi
> and qcom,sm8650-camss.yaml dt bindings documentation, thanks to Bryan,
> * added the fourth interrupt cell value needed for v6.15, thanks to Neil,
> * added a given Reviewed-by tag to one of the patches, thanks to Bryan,
> * rebased for v6.16.
>
>
> Vladimir Zapolskiy (4):
> dt-bindings: media: Describe Qualcomm SM8650 CAMSS IP
> media: qcom: camss: Add Qualcomm SM8650 CAMSS support
> media: qcom: camss: Add CSIPHY 2.2.0 lane configuration for SM8650
> arm64: dts: qcom: sm8650: Add CAMSS device tree node
>
> .../bindings/media/qcom,sm8650-camss.yaml | 375 ++++++++++++++++++
> arch/arm64/boot/dts/qcom/sm8650.dtsi | 180 +++++++++
> .../qcom/camss/camss-csiphy-3ph-1-0.c | 102 +++++
> drivers/media/platform/qcom/camss/camss-vfe.c | 2 +
> drivers/media/platform/qcom/camss/camss.c | 326 +++++++++++++++
> drivers/media/platform/qcom/camss/camss.h | 1 +
> 6 files changed, 986 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/media/qcom,sm8650-camss.yaml
>
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8650-QRD
^ permalink raw reply [flat|nested] 11+ messages in thread